[Linaro-uefi,1/6] Platforms/AMD/Styx: remove incorrect timer frequency

Message ID 20170623183045.21494-2-ard.biesheuvel@linaro.org
State Superseded
Headers show
Series
  • Platforms/AMD/Styx: various Cello related fixes
Related show

Commit Message

Ard Biesheuvel June 23, 2017, 6:30 p.m.
The ARM generic timer needs to be programmed with the actual frequency
of the input clock, but this can only be done from the most privileged
execution mode implemented by the hardware. UEFI on AArch64 usually
executes in EL2, which is not the most privileged execution mode in most
cases, and so the timer driver is set up to deal with this: no attempt
is made to program the PCD value PcdArmArchTimerFreqInHz into the frequency
register. However, a non-zero PCD value is still treated as an override
for the register value, in case the programmed value is known to be
incorrect.

However, on the various Styx based platforms, the PCD value is set to
an incorrect non-zero value, and so the routines that convert time delays
into cycle counts are off by 33% (187.5 MHz vs 250 MHz). This may affect
timeouts related to SATA link training, and other low level routines that
rely on accurate timekeeping.

So remove the explicit PCD settings, so they default to 0, letting the
driver use the programmed value instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc                 | 5 -----
 Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc | 5 -----
 Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc         | 5 -----
 3 files changed, 15 deletions(-)

Patch

diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
index f068713bf0b8..ddb944d0beb4 100644
--- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
+++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
@@ -400,11 +400,6 @@  DEFINE DO_KCS    = 0
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
 
   #
-  # ARM Architectual Timer Frequency
-  #
-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
-
-  #
   # Cello has 2 SATA ports on the first controller.
   #
   gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2
diff --git a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc
index b1a7cfd4c4a8..f6d2d37014dd 100644
--- a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc
+++ b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc
@@ -402,11 +402,6 @@  DEFINE DO_KCS       = 1
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
 
   #
-  # ARM Architectual Timer Frequency
-  #
-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
-
-  #
   # 2 ports active on Overdrive 1000
   #
   gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
index 98f5c9452dcd..7ac3ce3760fa 100644
--- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
+++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
@@ -409,11 +409,6 @@  DEFINE DO_KCS       = 1
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
 
   #
-  # ARM Architectual Timer Frequency
-  #
-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
-
-  #
   # Overdrive B1 has 14 SATA ports across 2 controllers.
   #
   gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8