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[209.132.180.67]) by mx.google.com with ESMTP id b12si1658852plk.568.2017.06.29.22.47.09; Thu, 29 Jun 2017 22:47:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=D1st9FoL; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751944AbdF3Fq5 (ORCPT + 6 others); Fri, 30 Jun 2017 01:46:57 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:33311 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751333AbdF3Fq4 (ORCPT ); Fri, 30 Jun 2017 01:46:56 -0400 Received: by mail-pg0-f51.google.com with SMTP id f127so58488422pgc.0 for ; Thu, 29 Jun 2017 22:46:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fsLLYHBPsKKb3mLCINlcyWXRGaZKhhkZ1uczRcer8+E=; b=D1st9FoLBFC4Za2WgU3p2+GZJedey80aG+b1rVtReiOgENQ3MNNnQiob0qq3S2kOVk 0AwMEdEaHlfrdYV3Df7eAUxlZlIrVfVYZ2kW6lkO5gBqxRxtx3qeXeN61JTZxvqJbvRr 0gdTrLq7bSGyrUq7yfPo35SxK2Vf4VPTM1fJs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fsLLYHBPsKKb3mLCINlcyWXRGaZKhhkZ1uczRcer8+E=; b=ddR93YvUerzCqH18gkmoTKLm5V3iJhxr9p+Nip0mjl5eHgEIf84OGyBSOThq/B68+v M5F7Qj1JUEdkcQ8rPDfDJNbYXLy1/n+Vj1yh6v254Q1ZuE0Sbo/pNdeFqrHBTN1dlRqH 560Gb6oeC7RN5Q6oeftTTXj9e4OIUNz4JKVCza/XruAlTLV798XOhcnyZlgCGKyZavLB 0EPdgb3Ej8gwcy6akB4oREhLLOaFrll6t6wPfpor3MrnO6OcNI3S3VLr8Oocv+SdLUBF xWpvNioV7kOEP3wg7UhwJd5/BBdmbJRizvuFpDZDmSRMmSLE1AO127UtTC+pFlOXTrxv ZzQg== X-Gm-Message-State: AKS2vOwk7KUcFOT6942BPnWBE5fYEY1ynmBMQ3TXBC9VPIVzDKT0RaHb xc8OvX3hiA/G+Mlh X-Received: by 10.84.212.151 with SMTP id e23mr22617577pli.115.1498801615303; Thu, 29 Jun 2017 22:46:55 -0700 (PDT) Received: from localhost.localdomain ([106.51.129.233]) by smtp.gmail.com with ESMTPSA id a187sm11405550pgc.37.2017.06.29.22.46.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Jun 2017 22:46:54 -0700 (PDT) From: Amit Pundir To: Greg KH Cc: Stable , Felix Fietkau , Alban Bedel , sergei.shtylyov@cogentembedded.com, linux-mips@linux-mips.org, Ralf Baechle Subject: [PATCH for-4.4 03/16] MIPS: ath79: fix regression in PCI window initialization Date: Fri, 30 Jun 2017 11:16:27 +0530 Message-Id: <1498801600-20896-4-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498801600-20896-1-git-send-email-amit.pundir@linaro.org> References: <1498801600-20896-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Felix Fietkau commit 9184dc8ffa56844352b3b9860e562ec4ee41176f upstream. ath79_ddr_pci_win_base has the type void __iomem *, so register offsets need to be a multiple of 4. Cc: Alban Bedel Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface") Signed-off-by: Felix Fietkau Cc: sergei.shtylyov@cogentembedded.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13258/ Signed-off-by: Ralf Baechle Signed-off-by: Amit Pundir --- arch/mips/ath79/common.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index 3cedd1f95e0f..8ae4067a5eda 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -76,14 +76,14 @@ void ath79_ddr_set_pci_windows(void) { BUG_ON(!ath79_ddr_pci_win_base); - __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0); - __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1); - __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2); - __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3); - __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4); - __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5); - __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6); - __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7); + __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); + __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); + __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); + __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); + __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); + __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); + __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); + __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); } EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);