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[198.145.21.10]) by mx.google.com with ESMTPS id j66si11131526pfe.51.2017.07.02.19.48.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Jul 2017 19:48:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.b=azQYzlBX; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 48D1021CAD9B8; Sun, 2 Jul 2017 19:47:04 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-pg0-x230.google.com (mail-pg0-x230.google.com [IPv6:2607:f8b0:400e:c05::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B3A8921A00ACB for ; Sun, 2 Jul 2017 19:47:03 -0700 (PDT) Received: by mail-pg0-x230.google.com with SMTP id j186so87816349pge.2 for ; Sun, 02 Jul 2017 19:48:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=gtP7/e707Qph7BzVkCAjIc7Lvd3DqlaPEqCTwgR0l6g=; b=azQYzlBXzxnMauEfFj56nb4IgUuf3hVFJXXwR/vR3xko/kz4J68Zp66aCdTgDmtR2o LrQ0eHm8pf6xFyIkgS8TWh/rqGvdFBjIKMGEdoAezduUkFghJu93ArsVpWdBJX+yzKyk TKBWeSoocr5IljuMMhunJMoIkSrrtSv8tuxho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=gtP7/e707Qph7BzVkCAjIc7Lvd3DqlaPEqCTwgR0l6g=; b=rJpV9y1Cgps22zJdH983I8e3Clttj5QdJqILsKBJ1YhZ2nj1wL1ocG+Mjlauxajr5O Epbkx/5UhjL6n64js+vHBRBjq4UHOxa8wsrQLfrNlLNJ+TLtrU02Ka5w4g0GuLOEO4I6 yVXzUmih1y04Pqm0R4ikLrnJ7vKWPvmdhl4FMyJ8Oh5A+5c9NWmxVWucJ1zT13xQJbhZ ybg6r4LbtC5mogKOGZnTljGsAeZ27vYtZ/FdsC2wOE/ZSh7YJYtFf+wwDwmDAVp0EeVJ RsP3EFFXJMy2beY5WaZkkVM57ec1+Z2vPr2FbgsSvd2HQryvE9kcsQ5vNk/cpw35lytq 5KEA== X-Gm-Message-State: AIVw111G9qYpwUwsm/XoFgBCDPwB4+XwALiTQry7ZA/GIxfU5dwxAECG Oe3PSe9EgOWYB68B X-Received: by 10.98.193.197 with SMTP id i188mr7696763pfg.215.1499050120067; Sun, 02 Jul 2017 19:48:40 -0700 (PDT) Received: from localhost.localdomain ([113.53.228.63]) by smtp.gmail.com with ESMTPSA id 66sm27691555pgh.59.2017.07.02.19.48.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Jul 2017 19:48:39 -0700 (PDT) From: Jun Nie To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, edk2-devel@lists.01.org, evan.lloyd@arm.com, Alexei.Fedorov@arm.com Date: Mon, 3 Jul 2017 10:48:26 +0800 Message-Id: <1499050106-12875-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Subject: [edk2] [PATCH] ArmPlatformPkg: Support different reg offset to PL011 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jason.liu@linaro.org, shawn.guo@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" ZTE SoC has different offset for some registers and bits. Add a macro flag to undef/redef those value. The macro flag can be enabled in BuildOptions section of platform.dsc. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie --- ArmPlatformPkg/Include/Drivers/PL011Uart.h | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/Include/Drivers/PL011Uart.h b/ArmPlatformPkg/Include/Drivers/PL011Uart.h index d5e88e8..87fab60 100644 --- a/ArmPlatformPkg/Include/Drivers/PL011Uart.h +++ b/ArmPlatformPkg/Include/Drivers/PL011Uart.h @@ -40,6 +40,34 @@ #define UARTPID2 0xFE8 #define UARTPID3 0xFEC +#ifdef ZX_PL011_FLAG +#undef UARTDR +#undef UARTFR +#undef UARTIBRD +#undef UARTFBRD +#undef UARTLCR_H +#undef UARTCR +#undef UARTIFLS +#undef UARTIMSC +#undef UARTRIS +#undef UARTMIS +#undef UARTICR +#undef UARTDMACR + +#define UARTDR 0x004 +#define UARTFR 0x014 +#define UARTIBRD 0x024 +#define UARTFBRD 0x028 +#define UARTLCR_H 0x030 +#define UARTCR 0x034 +#define UARTIFLS 0x038 +#define UARTIMSC 0x040 +#define UARTRIS 0x044 +#define UARTMIS 0x048 +#define UARTICR 0x04c +#define UARTDMACR 0x050 +#endif + // Data status bits #define UART_DATA_ERROR_MASK 0x0F00 @@ -57,6 +85,18 @@ #define PL011_UARTFR_DSR (1 << 1) // Data set ready #define PL011_UARTFR_CTS (1 << 0) // Clear to send +#ifdef ZX_PL011_FLAG +#undef PL011_UARTFR_RI +#undef PL011_UARTFR_BUSY +#undef PL011_UARTFR_DSR +#undef PL011_UARTFR_CTS + +#define PL011_UARTFR_RI 0x001 // Ring indicator +#define PL011_UARTFR_BUSY 0x100 // UART busy +#define PL011_UARTFR_DSR 0x008 // Data set ready +#define PL011_UARTFR_CTS 0x002 // Clear to send +#endif + // Flag reg bits - alternative names #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE #define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF