[edk2,platforms:,10/10] Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slave

Message ID 1499174653-330-11-git-send-email-mw@semihalf.com
State New
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Series
  • Untitled series #2711
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Commit Message

Marcin Wojtas July 4, 2017, 1:24 p.m.
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>


Add support for PHY_TYPE_SATA2 and PHY_TYPE_SATA3, which map to the
SATA ports on the second CP110's AHCI controller.

While at it, add a missing newline in the debug output to make it more
legible.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Signed-off-by: Marcin Wojtas <mw@semihalf.com>

---
 Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

-- 
2.7.4

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Comments

Leif Lindholm July 4, 2017, 3:38 p.m. | #1
On Tue, Jul 04, 2017 at 03:24:13PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> 

> Add support for PHY_TYPE_SATA2 and PHY_TYPE_SATA3, which map to the

> SATA ports on the second CP110's AHCI controller.

> 

> While at it, add a missing newline in the debug output to make it more

> legible.


Now now, one logical change per patch please.

> 

> Contributed-under: TianoCore Contribution Agreement 1.0

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

> ---

>  Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 20 +++++++++++---------

>  1 file changed, 11 insertions(+), 9 deletions(-)

> 

> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

> index de35265..5180060 100755

> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

> @@ -54,21 +54,23 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;

>   */

>  COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {

>    /* Lane 0 */

> -  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}}},

> +  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4},

> +    {COMPHY_TYPE_SATA3, 0x4}}},

>    /* Lane 1 */

> -  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},

> +  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4},

> +    {COMPHY_TYPE_SATA2, 0x4}}},

>    /* Lane 2 */

>    {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_TYPE_RXAUI0, 0x1},

> -    {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},

> +    {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},

>    /* Lane 3 */

> -  {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2},

> -    {COMPHY_TYPE_SATA1, 0x4}}},

> +  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2},

> +    {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},

>    /* Lane 4 */

> -  {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2},

> +  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2},

>      {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}},

>    /* Lane 5 */

> -  {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2},

> -    {COMPHY_TYPE_SATA1, 0x4}}},

> +  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2},

> +    {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},

>  };

>  

>  COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {

> @@ -1840,7 +1842,7 @@ ComPhyCp110Init (

>        break;

>      }

>      if (EFI_ERROR(Status)) {

> -      DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status));

> +      DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x\n", Lane, Status));


Please drop this hunk. Submit it separately if you care enough.

/
    Leif

>        PtrComPhyMap->Type = COMPHY_TYPE_UNCONNECTED;

>      }

>    }

> -- 

> 2.7.4

> 

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Ard Biesheuvel July 4, 2017, 4:02 p.m. | #2
On 4 July 2017 at 16:38, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Tue, Jul 04, 2017 at 03:24:13PM +0200, Marcin Wojtas wrote:

>> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

>>

>> Add support for PHY_TYPE_SATA2 and PHY_TYPE_SATA3, which map to the

>> SATA ports on the second CP110's AHCI controller.

>>

>> While at it, add a missing newline in the debug output to make it more

>> legible.

>

> Now now, one logical change per patch please.

>

>>

>> Contributed-under: TianoCore Contribution Agreement 1.0

>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

>> ---

>>  Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 20 +++++++++++---------

>>  1 file changed, 11 insertions(+), 9 deletions(-)

>>

>> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

>> index de35265..5180060 100755

>> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

>> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

>> @@ -54,21 +54,23 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;

>>   */

>>  COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {

>>    /* Lane 0 */

>> -  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}}},

>> +  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4},

>> +    {COMPHY_TYPE_SATA3, 0x4}}},

>>    /* Lane 1 */

>> -  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},

>> +  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4},

>> +    {COMPHY_TYPE_SATA2, 0x4}}},

>>    /* Lane 2 */

>>    {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_TYPE_RXAUI0, 0x1},

>> -    {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},

>> +    {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},

>>    /* Lane 3 */

>> -  {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2},

>> -    {COMPHY_TYPE_SATA1, 0x4}}},

>> +  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2},

>> +    {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},

>>    /* Lane 4 */

>> -  {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2},

>> +  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2},

>>      {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}},

>>    /* Lane 5 */

>> -  {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2},

>> -    {COMPHY_TYPE_SATA1, 0x4}}},

>> +  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2},

>> +    {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},

>>  };

>>

>>  COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {

>> @@ -1840,7 +1842,7 @@ ComPhyCp110Init (

>>        break;

>>      }

>>      if (EFI_ERROR(Status)) {

>> -      DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status));

>> +      DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x\n", Lane, Status));

>

> Please drop this hunk. Submit it separately if you care enough.

>


Yeah, that's my bad. It was in my patch, which I never intended to
propose as-is.
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Patch

diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
index de35265..5180060 100755
--- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -54,21 +54,23 @@  DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
  */
 COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
   /* Lane 0 */
-  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}}},
+  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4},
+    {COMPHY_TYPE_SATA3, 0x4}}},
   /* Lane 1 */
-  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},
+  {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4},
+    {COMPHY_TYPE_SATA2, 0x4}}},
   /* Lane 2 */
   {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_TYPE_RXAUI0, 0x1},
-    {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},
+    {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
   /* Lane 3 */
-  {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2},
-    {COMPHY_TYPE_SATA1, 0x4}}},
+  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2},
+    {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},
   /* Lane 4 */
-  {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2},
+  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2},
     {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}},
   /* Lane 5 */
-  {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2},
-    {COMPHY_TYPE_SATA1, 0x4}}},
+  {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2},
+    {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},
 };
 
 COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
@@ -1840,7 +1842,7 @@  ComPhyCp110Init (
       break;
     }
     if (EFI_ERROR(Status)) {
-      DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status));
+      DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x\n", Lane, Status));
       PtrComPhyMap->Type = COMPHY_TYPE_UNCONNECTED;
     }
   }