From patchwork Tue Jul 4 14:48:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 106991 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1097748qge; Tue, 4 Jul 2017 07:58:27 -0700 (PDT) X-Received: by 10.200.58.161 with SMTP id x30mr47238276qte.69.1499180306978; Tue, 04 Jul 2017 07:58:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499180306; cv=none; d=google.com; s=arc-20160816; b=STiJ+AHD4Gu5ZMatuWOa2upWtkzYKCyzAlDJGe2CzoGUVhSqbN6VGZvYB2z0QAegY0 6/4atdiN7+DqYExG3A9g8RDP8ijNV7LjoEzySErsCmHy245wuvJMZ9tRlqBf49kmiWpC sPT0vgjN9g3privnUaUWCO4p2RQFAABSy0epPdCv14Zts7O/nOIj2F+KL8oqV1qEmzNP m5e+Tma2DENDhX49QIpGFhmbnI9Jo0humEdINrg3aR07etFDcZstHSIDYrbQ3/4LGfRp Pe/0OeWAu22SjKggqXJtrIyMqW86nqW6DeY/KnEEBoVAZYJp7KvIcx7a87jI44KmumJg xKsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Xw1vcWhbLr05h9Koc4Bqo/GgakN277h/NJ+a1cmDMYA=; b=hdQkq6YxMHPlvo3Xf5bt2Y+ZitBeM97o64ePNOgl7E981vuHz42cxzgChV6igOdpLU 0s47UMnl1BZqG77wECHouWMbHAQyA9XllKeNJplK8ANA4ijs5OJGfyGAYYRsPpVsQ4Dl +eM6UL7kzhOQIuu+v68uuzvkvMwg5xpCIlocczpGlXMRCbACxg5IEem6YTlX85mmoMHq 8I6eL909kPwf0tjdCq+Xbn5cs3tUmB8A4vsAQjnLa/AMdf+1/ID9IsOkIVlb4/9qa1bu 3elQxzjGBISSMJaH62MToxU7EGSxHCebG9P/DFnqlVw3KQIwHDDZ9PRGKpDM3crLg2sc CLsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.b=d87kt1aI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id u10si17482676qki.371.2017.07.04.07.58.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 04 Jul 2017 07:58:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.b=d87kt1aI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41817 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSPHU-0000kE-Bd for patch@linaro.org; Tue, 04 Jul 2017 10:58:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37361) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSPD6-00052p-RU for qemu-devel@nongnu.org; Tue, 04 Jul 2017 10:53:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSPD3-0004em-0E for qemu-devel@nongnu.org; Tue, 04 Jul 2017 10:53:52 -0400 Received: from mail-wr0-x22e.google.com ([2a00:1450:400c:c0c::22e]:34103) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dSPD2-0004eI-Mn for qemu-devel@nongnu.org; Tue, 04 Jul 2017 10:53:48 -0400 Received: by mail-wr0-x22e.google.com with SMTP id 77so250356011wrb.1 for ; Tue, 04 Jul 2017 07:53:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xw1vcWhbLr05h9Koc4Bqo/GgakN277h/NJ+a1cmDMYA=; b=d87kt1aILp0Z+M2XXWhpUT9fLus02U3MvZltGK2H7Tw9NXP41jpyzwaWbS+Ub5Z3ul +/sA62vi8kdbnUqc5cBxIhhRyThI7aMhfTTiYhChwDn8OmU+tQVVefOkNlEuWTpdMt/D eMTaGq+3Qs65CIODYiFdoKDsAY9+ihK+eMLpg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xw1vcWhbLr05h9Koc4Bqo/GgakN277h/NJ+a1cmDMYA=; b=uZqbjXyQeoCow98Eu6S48eoYs3JjDWW/YRvgjVdaoUQAsixT+/sGxkb+vB7A557Vdd W2vzRRWyFHhRi+sZ5Foap6Xz6gS8KPROi91aXQV/9h7c3/85MnhafubCTZTBhexhCEe8 fHSALq9ywctmSPNxzlZ4oQHwADoKSR4IF/e19m1IEvFMqTGU1dvStmPnF+Mc8s26O3y9 PIlyRSYFoCrObHzsqNhbSjQb2oWcLAD+ChF/iWl+PQIbXCokYHFwjhpNOQOBNDML3zNf 7754ajt4yG2px6zrCmL0oueeAAtSNKbyYQ5Q6opgs9zmsBb2fM5/ghCz41ZZh4F7C0P9 pURA== X-Gm-Message-State: AKS2vOyoyvdiQjcO1hl2X0u/7tvJlMHD/6222AlbkYkMxGDOL3uXWfxS oW9vHQzG6c053iOt X-Received: by 10.223.164.218 with SMTP id h26mr40361330wrb.100.1499180027357; Tue, 04 Jul 2017 07:53:47 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 13sm16204040wrl.57.2017.07.04.07.53.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jul 2017 07:53:46 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 40F023E2201; Tue, 4 Jul 2017 15:49:11 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Tue, 4 Jul 2017 15:48:59 +0100 Message-Id: <20170704144859.17644-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170704144859.17644-1-alex.bennee@linaro.org> References: <20170704144859.17644-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RISU PATCH 11/11] aarch64.risu: update AdvancedSIMD across lanes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" - sorted alphabetically - aligned the instructions patterns - adding half-precision F[MAX|MIN][NMV|V] - add @AdvSIMDAcrossVector group Signed-off-by: Alex Bennée --- aarch64.risu | 90 +++++++++++++++++++++++++++++++++--------------------------- 1 file changed, 49 insertions(+), 41 deletions(-) -- 2.13.0 diff --git a/aarch64.risu b/aarch64.risu index 5450cd3..215882e 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -1955,50 +1955,58 @@ ZIP2 A64_V 0 Q:1 001110 size:2 0 rm:5 0 111 10 rn:5 rd:5 \ # ReservedValue: break the !($size == 3 && $Q == 0) constraint ZIP2_RES A64_V 0 0 001110 11 0 rm:5 0 111 10 rn:5 rd:5 -# C3.6.4 AdvSIMD across lanes +# C4-286 AdvSIMD across vector lanes # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 12 11 10 9 5 4 0 # 0 Q U 0 1 1 1 0 size 1 1 0 0 0 opcode 1 0 Rn Rd +@AdvSIMDAcrossVector + +ADDV A64_V 0 Q:1 0 01110 s:2 11000 11011 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +ADDV_RES A64_V 0 0 0 01110 10 11000 11011 10 rn:5 rd:5 + +FMAXNMV A64_V 0 1 1 01110 00 11000 01100 10 rn:5 rd:5 +FMAXV A64_V 0 1 1 01110 00 11000 01111 10 rn:5 rd:5 +FMINNMV A64_V 0 1 1 01110 10 11000 01100 10 rn:5 rd:5 +FMINV A64_V 0 1 1 01110 10 11000 01111 10 rn:5 rd:5 + +# ARMv8.2 Half-precision variants +FMAXNMV_FP16 A64_V 0 q:1 0 01110 00 11000 01100 10 rn:5 rd:5 +FMAXV_FP16 A64_V 0 q:1 0 01110 00 11000 01111 10 rn:5 rd:5 +FMINNMV_FP16 A64_V 0 q:1 0 01110 10 11000 01100 10 rn:5 rd:5 +FMINV_FP16 A64_V 0 q:1 0 01110 10 11000 01111 10 rn:5 rd:5 + +SADDLV A64_V 0 Q:1 0 01110 s:2 11000 00011 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +SADDLV_RES A64_V 0 0 0 01110 10 11000 00011 10 rn:5 rd:5 + +SMAXV A64_V 0 Q:1 0 01110 s:2 11000 01010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +SMAXV_RES A64_V 0 0 0 01110 10 11000 01010 10 rn:5 rd:5 + +SMINV A64_V 0 Q:1 0 01110 s:2 11000 11010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +SMINV_RES A64_V 0 0 0 01110 10 11000 11010 10 rn:5 rd:5 + +UADDLV A64_V 0 Q:1 1 01110 s:2 11000 00011 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +UADDLV_RES A64_V 0 0 1 01110 10 11000 00011 10 rn:5 rd:5 + +UMAXV A64_V 0 Q:1 1 01110 s:2 11000 01010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +UMAXV_RES A64_V 0 0 1 01110 10 11000 01010 10 rn:5 rd:5 + +UMINV A64_V 0 Q:1 1 01110 s:2 11000 11010 10 rn:5 rd:5 \ +!constraints { $s < 2 || ($s == 2 && $Q == 1); } +# ReservedValue: break the constraint (s==2) => (Q=1) +UMINV_RES A64_V 0 0 1 01110 10 11000 11010 10 rn:5 rd:5 -SADDLV A64_V 0 Q:1 0 01110 size:2 11000 00011 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -SADDLV_RES A64_V 0 0 0 01110 10 11000 00011 10 rn:5 rd:5 - -SMAXV A64_V 0 Q:1 0 01110 size:2 11000 01010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -SMAXV_RES A64_V 0 0 0 01110 10 11000 01010 10 rn:5 rd:5 - -SMINV A64_V 0 Q:1 0 01110 size:2 11000 11010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -SMINV_RES A64_V 0 0 0 01110 10 11000 11010 10 rn:5 rd:5 - -ADDV A64_V 0 Q:1 0 01110 size:2 11000 11011 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -ADDV_RES A64_V 0 0 0 01110 10 11000 11011 10 rn:5 rd:5 - -UADDLV A64_V 0 Q:1 1 01110 size:2 11000 00011 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -UADDLV_RES A64_V 0 0 1 01110 10 11000 00011 10 rn:5 rd:5 - -UMAXV A64_V 0 Q:1 1 01110 size:2 11000 01010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -UMAXV_RES A64_V 0 0 1 01110 10 11000 01010 10 rn:5 rd:5 - -UMINV A64_V 0 Q:1 1 01110 size:2 11000 11010 10 rn:5 rd:5 \ -!constraints { $size < 2 || ($size == 2 && $Q == 1); } -# ReservedValue: break the constraint (size==2) => (Q=1) -UMINV_RES A64_V 0 0 1 01110 10 11000 11010 10 rn:5 rd:5 - -FMAXNMV A64_V 0 1 1 01110 00 11000 01100 10 rn:5 rd:5 -FMAXV A64_V 0 1 1 01110 00 11000 01111 10 rn:5 rd:5 - -FMINNMV A64_V 0 1 1 01110 10 11000 01100 10 rn:5 rd:5 -FMINV A64_V 0 1 1 01110 10 11000 01111 10 rn:5 rd:5 +@ # C3.6.5 AdvSIMD copy # 31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 11 10 9 5 4 0