[edk2,platforms:,v2,10/10] Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slave

Message ID 1499205732-12445-3-git-send-email-mw@semihalf.com
State New
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Series
  • Untitled series #2721
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Commit Message

Marcin Wojtas July 4, 2017, 10:02 p.m.
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>


Add support for COMPHY_TYPE_SATA2 and COMPHY_TYPE_SATA3, which map
to the SATA ports on the second CP110's AHCI controller.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Signed-off-by: Marcin Wojtas <mw@semihalf.com>

---
 Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

-- 
1.8.3.1

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Comments

Leif Lindholm July 5, 2017, 4:38 p.m. | #1
On Wed, Jul 05, 2017 at 12:02:12AM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> 

> Add support for COMPHY_TYPE_SATA2 and COMPHY_TYPE_SATA3, which map

> to the SATA ports on the second CP110's AHCI controller.

> 

> Contributed-under: TianoCore Contribution Agreement 1.0

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> Signed-off-by: Marcin Wojtas <mw@semihalf.com>


Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>


> ---

>  Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 12 +++++++-----

>  1 file changed, 7 insertions(+), 5 deletions(-)

> 

> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

> index 6ef63a8..40a7b99 100755

> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c

> @@ -55,24 +55,26 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;

>  COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {

>    /* Lane 0 */

>    {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},

> -       {COMPHY_TYPE_SATA1, 0x4}}},

> +       {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},

>    /* Lane 1 */

>    {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},

> -       {COMPHY_TYPE_SATA0, 0x4}}},

> +       {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},

>    /* Lane 2 */

>    {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},

>         {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},

> -       {COMPHY_TYPE_SATA0, 0x4}}},

> +       {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},

>    /* Lane 3 */

>    {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},

> -       {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}},

> +       {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},

> +       {COMPHY_TYPE_SATA3, 0x4}}},

>    /* Lane 4 */

>    {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},

>         {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},

>         {COMPHY_TYPE_SGMII1, 0x1}}},

>    /* Lane 5 */

>    {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},

> -       {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}},

> +       {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},

> +       {COMPHY_TYPE_SATA3, 0x4}}},

>  };

>  

>  COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {

> -- 

> 1.8.3.1

> 

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diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 6ef63a8..40a7b99 100755
--- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -55,24 +55,26 @@  DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
 COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
   /* Lane 0 */
   {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},
-       {COMPHY_TYPE_SATA1, 0x4}}},
+       {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},
   /* Lane 1 */
   {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
-       {COMPHY_TYPE_SATA0, 0x4}}},
+       {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
   /* Lane 2 */
   {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},
        {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},
-       {COMPHY_TYPE_SATA0, 0x4}}},
+       {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
   /* Lane 3 */
   {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},
-       {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}},
+       {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
+       {COMPHY_TYPE_SATA3, 0x4}}},
   /* Lane 4 */
   {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},
        {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},
        {COMPHY_TYPE_SGMII1, 0x1}}},
   /* Lane 5 */
   {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
-       {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}},
+       {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
+       {COMPHY_TYPE_SATA3, 0x4}}},
 };
 
 COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {