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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q200sm1706348lfe.49.2017.07.04.15.02.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jul 2017 15:02:49 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 5 Jul 2017 00:02:12 +0200 Message-Id: <1499205732-12445-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1499205732-12445-1-git-send-email-mw@semihalf.com> References: <1499205732-12445-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 10/10] Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slave X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Add support for COMPHY_TYPE_SATA2 and COMPHY_TYPE_SATA3, which map to the SATA ports on the second CP110's AHCI controller. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c index 6ef63a8..40a7b99 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -55,24 +55,26 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { /* Lane 0 */ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, - {COMPHY_TYPE_SATA1, 0x4}}}, + {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}}, /* Lane 1 */ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, - {COMPHY_TYPE_SATA0, 0x4}}}, + {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}}, /* Lane 2 */ {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1}, - {COMPHY_TYPE_SATA0, 0x4}}}, + {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}}, /* Lane 3 */ {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, - {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}}, + {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}, + {COMPHY_TYPE_SATA3, 0x4}}}, /* Lane 4 */ {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, - {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}}, + {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}, + {COMPHY_TYPE_SATA3, 0x4}}}, }; COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {