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[209.132.180.67]) by mx.google.com with ESMTP id i5si1736017pfb.330.2017.07.08.13.03.37; Sat, 08 Jul 2017 13:03:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=OrVek8q7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753117AbdGHUDh (ORCPT + 6 others); Sat, 8 Jul 2017 16:03:37 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:36470 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753059AbdGHUDg (ORCPT ); Sat, 8 Jul 2017 16:03:36 -0400 Received: by mail-pf0-f176.google.com with SMTP id q86so31752022pfl.3 for ; Sat, 08 Jul 2017 13:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6hTAI8DAWiz0vhUOZMbAT9D0Wos1yUrfRbMCM+QEwHc=; b=OrVek8q7IDyd4WrcDZnlMbfD1mqCo8U0kWg35vsws7v7iZAQH6+mv70M6lDaPzIjk8 69FPwxCLzJ4c+BV1JmiEW0uQ/mO3ms3y7dc1oEdHPFmMhqZhj8fK/y/er5ttaQ2aGn4i xAjuZbtTDeWIltvxIA3Z8ogX/JDNccw6BbIOg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6hTAI8DAWiz0vhUOZMbAT9D0Wos1yUrfRbMCM+QEwHc=; b=e79Lw/YpbsqZloXWXfoRSVBtcq1jJ5A4eZ3HiXZAc1R8u4+C5EOiFa+ZkNMnQ++Ng9 dXTLueq0j64M8oerUjqW5/6ZOkx02+erdUpecQhAMEvwtm5RIykIweHxqDmOoDZ4D5Nr UJ1eI7WZr44jnDUOqKmDJYxMc0HqJFPjZkUlp0AvmCv7tMuk2gVPGyTtbHtR+Bs+XGhC nqVfrlM4rA1k6OdR+F1lxYsSeu2EReH6mOAA/iP2QLtbmd+vvRY1aUFCaIa8wcN0b3hX rl/CtbjXLgIcrOsDhNdcZwrg7fGO3rE8/VYVAsGg7Q9a9NffMcEH6Zo7KufeL+ekaExV f+yQ== X-Gm-Message-State: AIVw112WuAWlMxC9fVxC4yPlWzRGflUHLbJzm8CR5TkRAcuBl0znmXMl Y0UfVipVC9MfzlgOQyf21Q== X-Received: by 10.84.150.164 with SMTP id h33mr9773429plh.152.1499544215942; Sat, 08 Jul 2017 13:03:35 -0700 (PDT) Received: from localhost.localdomain ([106.51.234.165]) by smtp.gmail.com with ESMTPSA id m79sm1155703pfk.35.2017.07.08.13.03.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 08 Jul 2017 13:03:34 -0700 (PDT) From: Amit Pundir To: Greg KH , Eric Anholt Cc: Stable Subject: [PATCH for-4.4.y 3/5] drm/vc4: Fix setting of vertical timings in the CRTC. Date: Sun, 9 Jul 2017 01:33:19 +0530 Message-Id: <1499544201-12812-4-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499544201-12812-1-git-send-email-amit.pundir@linaro.org> References: <1499544201-12812-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Eric Anholt commit a7c5047d1ce178dd2b1fa577fc8909ad663d56d5 upstream. It looks like when I went to add the interlaced bits, I just took the existing PV_VERT* block and indented it, instead of copy and pasting it first. Without this, changing resolution never worked. Signed-off-by: Eric Anholt Signed-off-by: Amit Pundir --- drivers/gpu/drm/vc4/vc4_crtc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.13.0 diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 784a450d3e72..d0e34457aebd 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -213,6 +213,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) PV_HORZB_HFP) | VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE)); + CRTC_WRITE(PV_VERTA, + VC4_SET_FIELD(mode->vtotal - mode->vsync_end, + PV_VERTA_VBP) | + VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, + PV_VERTA_VSYNC)); + CRTC_WRITE(PV_VERTB, + VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, + PV_VERTB_VFP) | + VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE)); + if (interlace) { CRTC_WRITE(PV_VERTA_EVEN, VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,