From patchwork Sat Jul 8 20:03:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 107235 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1614650qge; Sat, 8 Jul 2017 13:03:43 -0700 (PDT) X-Received: by 10.98.17.84 with SMTP id z81mr37953493pfi.38.1499544223336; Sat, 08 Jul 2017 13:03:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499544223; cv=none; d=google.com; s=arc-20160816; b=XsNeS9Exu7hYsLvSZfN4DSKyXXzX5ZQwZuKUPAxv8NIpZz6dpabpGnRWwI5fg9OB6A HITqZlrEngxPlPhY2wGqqfsXTnnpMKnK2vsWnMbFRIEE/6SMJ5fPchdJyCrs0+NUUVeo jLfCO1D6ZThWaRvRchFe/C0GDxuuT1lFdZWOmzZZSlblASm3BaSwH6AFjBK4i+PFRwy4 an8MGIAyCFrxLQ1uW2gly9OpjHW6LEwJtC0IVnT+4a36aQKe7d3t9bpasx6ZbNsjd4qk rOoyclbCYbfjXvQwB3Ip4KWMb48l/o2+UY1yX9bKDMqM+Pc6+twJLUetRhDnJ43CNe6K zmJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=aRu7BF4AzIra8pTOBEWJUlNvWa+VcLmmowDFS2J5DEg=; b=A+Dwl3T8zw3STqkJwz1xl7U5NR9yofJZtv6P2whR10FYOFEHVqfVm12UkYsT501Ou8 jyrlSF/oynDyhPKOhtBAbKgtM4LDomUcCtniZu6jzgzeV6y+ViatfyeQzorbY4GUpS2F e8HYg5fYjarROrbTjCrteUu2tPnBP/vOT8lKHHIEujcFfGNAffHHLihpubP2GgFVxp5W IAI9PviGu5/HZaiyz56LEilG5l+Fj+kGXY9rF7tHLsCcvUvucONn7fwrzcMolTHOlmSm XHGgWJalLnv/uHYheKhy1/qOvE7h3kVIxxjDS6K8SGfy+RC45yVfKpPW3QAFwGOfd4E5 ERoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=KB/Q+C+Y; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i5si1736017pfb.330.2017.07.08.13.03.43; Sat, 08 Jul 2017 13:03:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=KB/Q+C+Y; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753124AbdGHUDm (ORCPT + 6 others); Sat, 8 Jul 2017 16:03:42 -0400 Received: from mail-pf0-f169.google.com ([209.85.192.169]:34140 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753059AbdGHUDm (ORCPT ); Sat, 8 Jul 2017 16:03:42 -0400 Received: by mail-pf0-f169.google.com with SMTP id q85so31774900pfq.1 for ; Sat, 08 Jul 2017 13:03:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aRu7BF4AzIra8pTOBEWJUlNvWa+VcLmmowDFS2J5DEg=; b=KB/Q+C+YXpAiKTvdJjrphXzCmERVmhNSiKf86jc5E0JEIDByR5PGvwtNPsCubapuHs aqOW6tuLFMpA7qie1ndNwGbo/gii1R40vKQUu+GnfFCqHULXRyCZyoC6GVkyS9Aie2XI nKvTiOkZldVNuBIm/v/n/UJ98T2Q6aH1pmSJs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aRu7BF4AzIra8pTOBEWJUlNvWa+VcLmmowDFS2J5DEg=; b=dRhil2rL8pD7HdaNfCazqNyH3zGVeX2gXaSbcqboE/pcZrchY2AFjBTWWlV7Bq2LBs uuYc16/NISsLtuYtESAaQF/vlfUTD5aqOGm+a29C/wBfXulmRMeIhMjM0Iu6UTKZ3fTt j/h5xKtB8iV4GPVRuABMk5X6sZ/QfluygOYtUf01XbxHBPVDiQs4lS5nrEzgD+SE1jHj wYFSGtVLrOYfWTKf5th6zXWWOmOT9j+h3UawhWZUWl1MKOVvXaIbYPrrf3+3X4bVUdfz kWtOcvyphoK5S/+coSXmmWpU9zI8jbVQ+ESaKcg3hn9IwI2LRCFneXHHdkCBPfhfauYF mbUQ== X-Gm-Message-State: AIVw1131HEKRiszbpoDcndKAnEAk3eqvB3Anet7cjRssfcFyDFLJmh/r UnDAEZGcnKNR8bAU X-Received: by 10.84.217.15 with SMTP id o15mr9946375pli.31.1499544221326; Sat, 08 Jul 2017 13:03:41 -0700 (PDT) Received: from localhost.localdomain ([106.51.234.165]) by smtp.gmail.com with ESMTPSA id m79sm1155703pfk.35.2017.07.08.13.03.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 08 Jul 2017 13:03:40 -0700 (PDT) From: Amit Pundir To: Greg KH , Eric Anholt Cc: Stable Subject: [PATCH for-4.4.y 5/5] drm/vc4: Bring HDMI up from power off if necessary. Date: Sun, 9 Jul 2017 01:33:21 +0530 Message-Id: <1499544201-12812-6-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499544201-12812-1-git-send-email-amit.pundir@linaro.org> References: <1499544201-12812-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Eric Anholt commit 851479ad5927b7b1aa141ca9dedb897a7bce2b1d upstream. If the firmware hadn't brought up HDMI for us, we need to do its power-on reset sequence (reset HD and and clear its STANDBY bits, reset HDMI, and leave the PHY disabled). Signed-off-by: Eric Anholt Signed-off-by: Amit Pundir --- drivers/gpu/drm/vc4/vc4_hdmi.c | 29 ++++++++++++++++++++++++++++- drivers/gpu/drm/vc4/vc4_regs.h | 2 ++ 2 files changed, 30 insertions(+), 1 deletion(-) -- 2.13.0 diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index e24ece43995f..ac65d19416b5 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -496,6 +496,16 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) goto err_put_i2c; } + /* This is the rate that is set by the firmware. The number + * needs to be a bit higher than the pixel clock rate + * (generally 148.5Mhz). + */ + ret = clk_set_rate(hdmi->hsm_clock, 163682864); + if (ret) { + DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); + goto err_unprepare_pix; + } + ret = clk_prepare_enable(hdmi->hsm_clock); if (ret) { DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", @@ -517,7 +527,24 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) vc4->hdmi = hdmi; /* HDMI core must be enabled. */ - WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0); + if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { + HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); + udelay(1); + HD_WRITE(VC4_HD_M_CTL, 0); + + HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); + + HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, + VC4_HDMI_SW_RESET_HDMI | + VC4_HDMI_SW_RESET_FORMAT_DETECT); + + HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); + + /* PHY should be in reset, like + * vc4_hdmi_encoder_disable() does. + */ + HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); + } drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, DRM_MODE_ENCODER_TMDS); diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index 06f5d298a651..45b8c18be5b0 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -470,6 +470,8 @@ #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 #define VC4_HD_M_CTL 0x00c +# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) +# define VC4_HD_M_RAM_STANDBY (3 << 4) # define VC4_HD_M_SW_RST BIT(2) # define VC4_HD_M_ENABLE BIT(0)