From patchwork Thu Jul 13 08:49:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 107617 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp1933104qge; Thu, 13 Jul 2017 01:51:01 -0700 (PDT) X-Received: by 10.84.232.134 with SMTP id i6mr8926618plk.248.1499935861414; Thu, 13 Jul 2017 01:51:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499935861; cv=none; d=google.com; s=arc-20160816; b=eojPaskgAwucf4C9SFOPz9uIvmky1y+KcY9W48K67BThosovQAKlQxN1+L0HjT/FFl qGqGml7dAizAYdFF00JDBXKPlls0N+UN7S/1WRKFD5GAcHODE11I4oQuWxPkbr51iWoj CjVzw0ccFeg6aYgBfs6b+3PpUERpT4rJY7ujXlhN+2EnDIqf8Ytv8rf1mjeTbdK5SiKI lsp5ZHsaaTV5wunBExm5sWDmu/iVwUt7TUTCN2HWoKXgfec38fMmI8SMKwuMYUUd38g5 aSyHx5e8CgzUyFC5jPSS+MytgJT1BiWJ5yJTMFByY+b8FJbr8R0beMfMghmTRmD9OBEP 7djg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=SSzitk/c6NjOpueX23hEf7wHcMl38bSO0ogoWq7+sJw=; b=BkHmvezZsdEaV20Bd3wAJoqmbuzOnIq8xz9QVS7X5z8b4OPibMR6eJZpCYXSOkTPUA FaD0l2oWtu3CD5k4+rvqtVT60HjlQ2yHaxNVvA5SsnK9U2lku7BRQj29sp9aRovT41jL KhdQBgbqZiSoHIy9KXGbNH7p/zFYz7sXO5548VoMP5e9b+tKwaBYw9c3SwAJb7yRQKqB RUr95ZiZhyWXKir9Y5F6uM0vDF4VlbWvEipvQDrLtJnN+vLvXu8pSqqR0aztFdmjyrdI D59T65s99qPeeKhXmwpKFPhiHRwO+AYHKm9FOwswq+Hnf8PXvinsDDQ9AnM5wJeiv3Jm f4Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.b=xozYjVRd; spf=pass (google.com: domain of gcc-patches-return-458022-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-458022-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id e3si4105954plb.11.2017.07.13.01.51.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 01:51:01 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-458022-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.b=xozYjVRd; spf=pass (google.com: domain of gcc-patches-return-458022-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-458022-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=lTgKJInRSPNokm1XnsyRz9XC3UHeq nbgqaYcsLCRsD55Z4/7N7Eg9l3S6VF4AddoOLDW8vaI5NNBVtrprN1xOKfqe3ibo OBXeHPf2Xc3JxJiRiUuZO6G9xRCIIYDFrhM0TQZcDaitL7jl5aCH/mOLG8pSQ6pv TqobH9AXY2UFhM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=Op+Ixwjw3mrWVCaIctdrhDzcFdU=; b=xoz YjVRdNV+Byn7v5doARqIMnsMiWUTYE3H+fhfOqxA3jDaS+XnVYhadWXVxrC2+aUx dFgGgJ3x248H6tmFs6h5Q2m2Zo7CK1cnSRyBWgOz+fdHFt1ZALV+GY7yz0/4XrNC JGMeSJNXgf47r2DPMOCGjyQYiYgIoWrWO2VQ/2dk= Received: (qmail 63928 invoked by alias); 13 Jul 2017 08:50:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60529 invoked by uid 89); 13 Jul 2017 08:49:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=guarding X-HELO: mail-wr0-f173.google.com Received: from mail-wr0-f173.google.com (HELO mail-wr0-f173.google.com) (209.85.128.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 13 Jul 2017 08:49:51 +0000 Received: by mail-wr0-f173.google.com with SMTP id 77so49638955wrb.1 for ; Thu, 13 Jul 2017 01:49:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=SSzitk/c6NjOpueX23hEf7wHcMl38bSO0ogoWq7+sJw=; b=iaKp1T4cmNzNebX4hO/ZZ8aT+GS6bbKQBW/veME24VyDcgmwsppHP6WQxcvYpI182t uFUnxUxsYBIqaE0zf7YvBiFAzbAJ/TrJ1loVQtlP34SG8xhI0z3p/lhb69vGs3ZaQrWG UF+HP3kPeZ9479KLM6t4MnuHprB2mqYi4FKfa/F0oczq+33xnbjOr38+J6TAufbe0K9K PfMs5/wBXhn9G8zRlSblFCjgSh9dtX3wtQZ5/v0l8B8De4+EX/npyuhPCZH0PpfObmWT 62u3OmBUaL+m7Ry8U74L402AaC5EGNoZjikeeGEokxbpIYBe9MhOAjZf3S5ThHeIup/+ YXTA== X-Gm-Message-State: AIVw110kd9g8T/8JokBWVkPlSMEturkvKubdQHH4nxVPIZ4Gy//qUGM0 1zggG7Td6gEOUDrx8c/zTw== X-Received: by 10.223.163.12 with SMTP id c12mr883295wrb.85.1499935789459; Thu, 13 Jul 2017 01:49:49 -0700 (PDT) Received: from localhost (92.40.249.184.threembb.co.uk. [92.40.249.184]) by smtp.gmail.com with ESMTPSA id b83sm3033117wmh.30.2017.07.13.01.49.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Jul 2017 01:49:48 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [31/77] Use scalar_int_mode for move2add References: <8760ewohsv.fsf@linaro.org> Date: Thu, 13 Jul 2017 09:49:46 +0100 In-Reply-To: <8760ewohsv.fsf@linaro.org> (Richard Sandiford's message of "Thu, 13 Jul 2017 09:35:44 +0100") Message-ID: <87fue0iuvp.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 The postreload move2add optimisations are specific to scalar integers. This patch adds an explicit check to the main guarding "if" and propagates the information through subroutines. gcc/ 2017-07-13 Richard Sandiford Alan Hayward David Sherwood * postreload.c (move2add_valid_value_p): Change the type of the mode parameter to scalar_int_mode. (move2add_use_add2_insn): Add a mode parameter and use it instead of GET_MODE (reg). (move2add_use_add3_insn): Likewise. (reload_cse_move2add): Update accordingly. Index: gcc/postreload.c =================================================================== --- gcc/postreload.c 2017-07-13 09:18:35.050126461 +0100 +++ gcc/postreload.c 2017-07-13 09:18:37.226935948 +0100 @@ -1692,7 +1692,7 @@ move2add_record_sym_value (rtx reg, rtx /* Check if REGNO contains a valid value in MODE. */ static bool -move2add_valid_value_p (int regno, machine_mode mode) +move2add_valid_value_p (int regno, scalar_int_mode mode) { if (reg_set_luid[regno] <= move2add_last_label_luid) return false; @@ -1723,21 +1723,21 @@ move2add_valid_value_p (int regno, machi return true; } -/* This function is called with INSN that sets REG to (SYM + OFF), - while REG is known to already have value (SYM + offset). +/* This function is called with INSN that sets REG (of mode MODE) + to (SYM + OFF), while REG is known to already have value (SYM + offset). This function tries to change INSN into an add instruction (set (REG) (plus (REG) (OFF - offset))) using the known value. It also updates the information about REG's known value. Return true if we made a change. */ static bool -move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) +move2add_use_add2_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off, + rtx_insn *insn) { rtx pat = PATTERN (insn); rtx src = SET_SRC (pat); int regno = REGNO (reg); - rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], - GET_MODE (reg)); + rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], mode); bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); bool changed = false; @@ -1759,7 +1759,7 @@ move2add_use_add2_insn (rtx reg, rtx sym else { struct full_rtx_costs oldcst, newcst; - rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); + rtx tem = gen_rtx_PLUS (mode, reg, new_src); get_full_set_rtx_cost (pat, &oldcst); SET_SRC (pat) = tem; @@ -1769,10 +1769,10 @@ move2add_use_add2_insn (rtx reg, rtx sym if (costs_lt_p (&newcst, &oldcst, speed) && have_add2_insn (reg, new_src)) changed = validate_change (insn, &SET_SRC (pat), tem, 0); - else if (sym == NULL_RTX && GET_MODE (reg) != BImode) + else if (sym == NULL_RTX && mode != BImode) { - machine_mode narrow_mode; - FOR_EACH_MODE_UNTIL (narrow_mode, GET_MODE (reg)) + scalar_int_mode narrow_mode; + FOR_EACH_MODE_UNTIL (narrow_mode, mode) { if (have_insn_for (STRICT_LOW_PART, narrow_mode) && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) @@ -1802,9 +1802,9 @@ move2add_use_add2_insn (rtx reg, rtx sym } -/* This function is called with INSN that sets REG to (SYM + OFF), - but REG doesn't have known value (SYM + offset). This function - tries to find another register which is known to already have +/* This function is called with INSN that sets REG (of mode MODE) to + (SYM + OFF), but REG doesn't have known value (SYM + offset). This + function tries to find another register which is known to already have value (SYM + offset) and change INSN into an add instruction (set (REG) (plus (the found register) (OFF - offset))) if such a register is found. It also updates the information about @@ -1812,7 +1812,8 @@ move2add_use_add2_insn (rtx reg, rtx sym Return true iff we made a change. */ static bool -move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) +move2add_use_add3_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off, + rtx_insn *insn) { rtx pat = PATTERN (insn); rtx src = SET_SRC (pat); @@ -1831,7 +1832,7 @@ move2add_use_add3_insn (rtx reg, rtx sym SET_SRC (pat) = plus_expr; for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) - if (move2add_valid_value_p (i, GET_MODE (reg)) + if (move2add_valid_value_p (i, mode) && reg_base_reg[i] < 0 && reg_symbol_ref[i] != NULL_RTX && rtx_equal_p (sym, reg_symbol_ref[i])) @@ -1921,8 +1922,10 @@ reload_cse_move2add (rtx_insn *first) pat = PATTERN (insn); /* For simplicity, we only perform this optimization on straightforward SETs. */ + scalar_int_mode mode; if (GET_CODE (pat) == SET - && REG_P (SET_DEST (pat))) + && REG_P (SET_DEST (pat)) + && is_a (GET_MODE (SET_DEST (pat)), &mode)) { rtx reg = SET_DEST (pat); int regno = REGNO (reg); @@ -1930,7 +1933,7 @@ reload_cse_move2add (rtx_insn *first) /* Check if we have valid information on the contents of this register in the mode of REG. */ - if (move2add_valid_value_p (regno, GET_MODE (reg)) + if (move2add_valid_value_p (regno, mode) && dbg_cnt (cse2_move2add)) { /* Try to transform (set (REGX) (CONST_INT A)) @@ -1950,7 +1953,8 @@ reload_cse_move2add (rtx_insn *first) && reg_base_reg[regno] < 0 && reg_symbol_ref[regno] == NULL_RTX) { - changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); + changed |= move2add_use_add2_insn (mode, reg, NULL_RTX, + src, insn); continue; } @@ -1967,7 +1971,7 @@ reload_cse_move2add (rtx_insn *first) else if (REG_P (src) && reg_set_luid[regno] == reg_set_luid[REGNO (src)] && reg_base_reg[regno] == reg_base_reg[REGNO (src)] - && move2add_valid_value_p (REGNO (src), GET_MODE (reg))) + && move2add_valid_value_p (REGNO (src), mode)) { rtx_insn *next = next_nonnote_nondebug_insn (insn); rtx set = NULL_RTX; @@ -1987,7 +1991,7 @@ reload_cse_move2add (rtx_insn *first) gen_int_mode (added_offset + base_offset - regno_offset, - GET_MODE (reg)); + mode); bool success = false; bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); @@ -1999,11 +2003,11 @@ reload_cse_move2add (rtx_insn *first) { rtx old_src = SET_SRC (set); struct full_rtx_costs oldcst, newcst; - rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); + rtx tem = gen_rtx_PLUS (mode, reg, new_src); get_full_set_rtx_cost (set, &oldcst); SET_SRC (set) = tem; - get_full_set_src_cost (tem, GET_MODE (reg), &newcst); + get_full_set_src_cost (tem, mode, &newcst); SET_SRC (set) = old_src; costs_add_n_insns (&oldcst, 1); @@ -2023,7 +2027,7 @@ reload_cse_move2add (rtx_insn *first) move2add_record_mode (reg); reg_offset[regno] = trunc_int_for_mode (added_offset + base_offset, - GET_MODE (reg)); + mode); continue; } } @@ -2059,16 +2063,16 @@ reload_cse_move2add (rtx_insn *first) /* If the reg already contains the value which is sum of sym and some constant value, we can use an add2 insn. */ - if (move2add_valid_value_p (regno, GET_MODE (reg)) + if (move2add_valid_value_p (regno, mode) && reg_base_reg[regno] < 0 && reg_symbol_ref[regno] != NULL_RTX && rtx_equal_p (sym, reg_symbol_ref[regno])) - changed |= move2add_use_add2_insn (reg, sym, off, insn); + changed |= move2add_use_add2_insn (mode, reg, sym, off, insn); /* Otherwise, we have to find a register whose value is sum of sym and some constant value. */ else - changed |= move2add_use_add3_insn (reg, sym, off, insn); + changed |= move2add_use_add3_insn (mode, reg, sym, off, insn); continue; }