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[209.132.180.67]) by mx.google.com with ESMTP id m2si4288973pfm.137.2017.07.13.08.10.07; Thu, 13 Jul 2017 08:10:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752737AbdGMPKF convert rfc822-to-8bit (ORCPT + 7 others); Thu, 13 Jul 2017 11:10:05 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:17966 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752435AbdGMPJM (ORCPT ); Thu, 13 Jul 2017 11:09:12 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v6DF3YcD028355; Thu, 13 Jul 2017 17:08:33 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 2bp8d60vte-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 13 Jul 2017 17:08:33 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 47AB53F; Thu, 13 Jul 2017 15:08:31 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node3.st.com [10.75.127.9]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 94FB82516; Thu, 13 Jul 2017 15:08:31 +0000 (GMT) Received: from SFHDAG3NODE1.st.com (10.75.127.7) by SFHDAG3NODE3.st.com (10.75.127.9) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Thu, 13 Jul 2017 17:08:31 +0200 Received: from SFHDAG3NODE1.st.com ([fe80::1166:1abb:aad4:5f86]) by SFHDAG3NODE1.st.com ([fe80::1166:1abb:aad4:5f86%20]) with mapi id 15.00.1178.000; Thu, 13 Jul 2017 17:08:30 +0200 From: Bich HEMON To: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre TORGUE , "Jiri Slaby" , "linux-serial@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" CC: Bich HEMON Subject: [PATCH 9/9] serial: stm32: add fifo support Thread-Topic: [PATCH 9/9] serial: stm32: add fifo support Thread-Index: AQHS++njIUaJNz+TCkiBB5oiKMYNTw== Date: Thu, 13 Jul 2017 15:08:30 +0000 Message-ID: <1499958494-19354-10-git-send-email-bich.hemon@st.com> References: <1499958494-19354-1-git-send-email-bich.hemon@st.com> In-Reply-To: <1499958494-19354-1-git-send-email-bich.hemon@st.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.49] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-13_08:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Gerald Baeza This patch adds fifo mode support for rx and tx. A fifo configuration is set in each port structure. Add has_fifo flag to usart configuration to use fifo only when possible. Signed-off-by: Gerald Baeza Signed-off-by: Bich Hemon --- drivers/tty/serial/stm32-usart.c | 7 +++++++ drivers/tty/serial/stm32-usart.h | 4 ++++ 2 files changed, 11 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 684cbe3..b16e7e7 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -468,6 +468,8 @@ static int stm32_startup(struct uart_port *port) } val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; + if (stm32_port->fifoen) + val |= USART_CR1_FIFOEN; stm32_set_bits(port, ofs->cr1, val); return 0; @@ -482,6 +484,8 @@ static void stm32_shutdown(struct uart_port *port) val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE; val |= BIT(cfg->uart_enable_bit); + if (stm32_port->fifoen) + val |= USART_CR1_FIFOEN; stm32_clr_bits(port, ofs->cr1, val); dev_pm_clear_wake_irq(port->dev); @@ -512,6 +516,8 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE; cr1 |= BIT(cfg->uart_enable_bit); + if (stm32_port->fifoen) + cr1 |= USART_CR1_FIFOEN; cr2 = 0; cr3 = 0; @@ -676,6 +682,7 @@ static int stm32_init_port(struct stm32_port *stm32port, port->dev = &pdev->dev; port->irq = platform_get_irq(pdev, 0); stm32port->wakeirq = platform_get_irq(pdev, 1); + stm32port->fifoen = stm32port->info->cfg.has_fifo; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); port->membase = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index 5984a66..ffc0c52 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -26,6 +26,7 @@ struct stm32_usart_config { u8 uart_enable_bit; /* USART_CR1_UE */ bool has_7bits_data; bool has_wakeup; + bool has_fifo; }; struct stm32_usart_info { @@ -94,6 +95,7 @@ struct stm32_usart_info stm32h7_info = { .uart_enable_bit = 0, .has_7bits_data = true, .has_wakeup = true, + .has_fifo = true, } }; @@ -159,6 +161,7 @@ struct stm32_usart_info stm32h7_info = { #define USART_CR1_EOBIE BIT(27) /* F7 */ #define USART_CR1_M1 BIT(28) /* F7 */ #define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27)) +#define USART_CR1_FIFOEN BIT(29) /* H7 */ /* USART_CR2 */ #define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */ @@ -253,6 +256,7 @@ struct stm32_port { int last_res; bool tx_dma_busy; /* dma tx busy */ bool hw_flow_control; + bool fifoen; int wakeirq; };