From patchwork Mon Jul 17 12:44:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 107916 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp4468262qge; Mon, 17 Jul 2017 05:47:05 -0700 (PDT) X-Received: by 10.55.78.85 with SMTP id c82mr25854113qkb.154.1500295625937; Mon, 17 Jul 2017 05:47:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500295625; cv=none; d=google.com; s=arc-20160816; b=bkwV7/x+PPO5hQJpEt6BSNachmKOGC91+wjP7Znq+j8SeslsJzItmYsidI5k3DQTFa p1iIth+5O49h2tUhyEvX7rcj51dD59pG1iFp33lMM7qDa2dd6RxCDO0qf0IU9JSi896Y C4GOiCoT4P6htwPvkfmZSzjW0rIlOYDZbxzxjDxspmNWttfRpUeT19RCx++m3IW2Sh0p INtxWI+JimIjNBoF6AHqwV5FSyhnm8F6s9z7A6L+ZR8N2eSWsZ1IyARvBot8eZCW1ODn MqAhcy+IueyYlQcLo9U+6hp94fpIW7lRBEnUTAPushLipFjSYT0H+iBqIhaH4SYh1ouY POrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=TkSFH3zjHQhbizyW1SaxfzJfGk3L+TR2sRcg05iiY7E=; b=QRT/0F9dOlGxCSfjk6hpF5KpTGuYIdwkurdmQZbhtN8JCx8Duo6LjBiiiNt9KpwXS4 pHKGEsQQxO9MV+tTwAdR7hRw7akz3svORRW5vgkCFUxBdrAq1055wf87gazNItWy2npk oXu4Mmcd3GMbWtrHy+lfA7xI/WuVsAfaGHqvWVJQYW5fh77LYyzZdwR3KY7UYXP3AVhH PDzp6zpZAHYKXX8uXF5w2rOuOgDl5X0GL8wc67y6rjCPoCW1Up63SkUPHyoCJG5Y7Lt5 e4YJz7FXBwcCDAvXU9qtMCPOFziuIBSTVpbRePF15sNWrhKVnbqVpyEaRRZMMiBRl3iF KIJQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j6si15467532qti.143.2017.07.17.05.47.05 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 17 Jul 2017 05:47:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dX5QV-0000db-Ck for patch@linaro.org; Mon, 17 Jul 2017 08:47:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dX5Oa-0007qh-S9 for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dX5Oa-0002Ct-16 for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37639) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dX5OZ-00029H-QG for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:03 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dX5OY-0003X2-W7 for qemu-devel@nongnu.org; Mon, 17 Jul 2017 13:45:03 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jul 2017 13:44:52 +0100 Message-Id: <1500295494-8991-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500295494-8991-1-git-send-email-peter.maydell@linaro.org> References: <1500295494-8991-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/18] hw/arm/mps2: Add SCC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the SCC to the MPS2 board models. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1500029487-14822-8-git-send-email-peter.maydell@linaro.org --- hw/arm/mps2.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 4121816..80ee79e 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -34,6 +34,7 @@ #include "hw/misc/unimp.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/timer/cmsdk-apb-timer.h" +#include "hw/misc/mps2-scc.h" typedef enum MPS2FPGAType { FPGA_AN385, @@ -44,6 +45,7 @@ typedef struct { MachineClass parent; MPS2FPGAType fpga_type; const char *cpu_model; + uint32_t scc_id; } MPS2MachineClass; typedef struct { @@ -60,6 +62,7 @@ typedef struct { MemoryRegion blockram_m2; MemoryRegion blockram_m3; MemoryRegion sram; + MPS2SCC scc; } MPS2MachineState; #define TYPE_MPS2_MACHINE "mps2" @@ -102,7 +105,7 @@ static void mps2_common_init(MachineState *machine) MPS2MachineState *mms = MPS2_MACHINE(machine); MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); MemoryRegion *system_memory = get_system_memory(); - DeviceState *armv7m; + DeviceState *armv7m, *sccdev; if (!machine->cpu_model) { machine->cpu_model = mmc->cpu_model; @@ -297,6 +300,16 @@ static void mps2_common_init(MachineState *machine) cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); + object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC); + sccdev = DEVICE(&mms->scc); + qdev_set_parent_bus(armv7m, sysbus_get_default()); + qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); + qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); + qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + object_property_set_bool(OBJECT(&mms->scc), true, "realized", + &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, @@ -319,6 +332,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; mmc->fpga_type = FPGA_AN385; mmc->cpu_model = "cortex-m3"; + mmc->scc_id = 0x41040000 | (385 << 4); } static void mps2_an511_class_init(ObjectClass *oc, void *data) @@ -329,6 +343,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data) mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; mmc->fpga_type = FPGA_AN511; mmc->cpu_model = "cortex-m3"; + mmc->scc_id = 0x4104000 | (511 << 4); } static const TypeInfo mps2_info = {