From patchwork Mon Jul 17 12:44:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 107920 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp4469361qge; Mon, 17 Jul 2017 05:48:11 -0700 (PDT) X-Received: by 10.55.100.206 with SMTP id y197mr10579019qkb.56.1500295691453; Mon, 17 Jul 2017 05:48:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500295691; cv=none; d=google.com; s=arc-20160816; b=dq2f6GMYHQIc+i2OETxWmxgq+/4zyMQ14on+dYYjyIDLADJzQIdoBguL6xLRLmLoiW vhLaUf7qnP/L8giLn2wtx03R/yaoZBz6NMYn0TehtA8x9X8WZI5qwfNO85q0kOJ9fQq8 bWhemiJeYGkTdA+gE3aToCXk4w6KgBKZRswnAa94z9Yf8sRUf2ewnG5yeHyTLhhOuHej THiqGLNHeIIVg9qGmng2KDM4Ehz6E+Km4yXdzRDI+KzD2UzM11YpdnzlMiqCPZ9Hqyt/ nEHthdvYq8qQLHxPRk6gGzvYAOEWSU4ksl7+wD0a9qU7RBhHFgAyURTeCsJsA8IW0hc4 LHZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=Ja/tKJXXOPdC9OadYkBej9x5EqMES8F+BSkWuU9tDis=; b=TpgQm4ROpftgvxWOyrL6Ym/505ykEbzeCQMc/DG3lT+iBfSlLyhdVGvmJ5D5fAywjB Pakd2wHwz6Ul+Xpam2Jjif9Z29tzkfsHduvMjDQcriNcYgCOYRttflp/eSDHjoqoXf/j R4ikxuNpX2jrPBENZh34y/fQtNFaOZsxH+FX5kLkkxdAc5aROZNfA0+gHy7C0/YugV1K o+uHfbrlYt+mNViU4gu+tBSR+leLmOKQ9Hlv3JnEUlDyM5FBZAjgSdM5O9htXJlFY7D8 uRy5tIhX31qA5f50Q0aDZfRobc2KUlgkX5MZwQnP9JALFKtFPJLzNRZyDK3AePVFGeZt k15g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n30si944495qtf.153.2017.07.17.05.48.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 17 Jul 2017 05:48:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50174 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dX5RY-0001gH-QR for patch@linaro.org; Mon, 17 Jul 2017 08:48:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59090) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dX5Od-0007tJ-Pc for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dX5Oc-0002Ef-NS for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:07 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37639) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dX5Oc-00029H-Ew for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dX5OX-0003VV-57 for qemu-devel@nongnu.org; Mon, 17 Jul 2017 13:45:01 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jul 2017 13:44:48 +0100 Message-Id: <1500295494-8991-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500295494-8991-1-git-send-email-peter.maydell@linaro.org> References: <1500295494-8991-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/18] hw/arm/mps2: Add UARTs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the UARTs to the MPS2 board models. Unfortunately the details of the wiring of the interrupts through various OR gates differ between AN511 and AN385 so this can't be purely a data-driven difference. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 1500029487-14822-4-git-send-email-peter.maydell@linaro.org --- hw/arm/mps2.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++++ hw/char/cmsdk-apb-uart.c | 2 +- 2 files changed, 89 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 22b33ff..9c8fa77 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -27,9 +27,12 @@ #include "qemu/error-report.h" #include "hw/arm/arm.h" #include "hw/arm/armv7m.h" +#include "hw/or-irq.h" #include "hw/boards.h" #include "exec/address-spaces.h" +#include "sysemu/sysemu.h" #include "hw/misc/unimp.h" +#include "hw/char/cmsdk-apb-uart.h" typedef enum MPS2FPGAType { FPGA_AN385, @@ -205,6 +208,91 @@ static void mps2_common_init(MachineState *machine) create_unimplemented_device("Ethernet", 0x40200000, 0x00100000); create_unimplemented_device("VGA", 0x41000000, 0x0200000); + switch (mmc->fpga_type) { + case FPGA_AN385: + { + /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. + * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. + */ + Object *orgate; + DeviceState *orgate_dev; + int i; + + orgate = object_new(TYPE_OR_IRQ); + object_property_set_int(orgate, 6, "num-lines", &error_fatal); + object_property_set_bool(orgate, true, "realized", &error_fatal); + orgate_dev = DEVICE(orgate); + qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); + + for (i = 0; i < 5; i++) { + static const hwaddr uartbase[] = {0x40004000, 0x40005000, + 0x40006000, 0x40007000, + 0x40009000}; + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; + /* RX irq number; TX irq is always one greater */ + static const int uartirq[] = {0, 2, 4, 18, 20}; + qemu_irq txovrint = NULL, rxovrint = NULL; + + if (i < 3) { + txovrint = qdev_get_gpio_in(orgate_dev, i * 2); + rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); + } + + cmsdk_apb_uart_create(uartbase[i], + qdev_get_gpio_in(armv7m, uartirq[i] + 1), + qdev_get_gpio_in(armv7m, uartirq[i]), + txovrint, rxovrint, + NULL, + uartchr, SYSCLK_FRQ); + } + break; + } + case FPGA_AN511: + { + /* The overflow IRQs for all UARTs are ORed together. + * Tx and Rx IRQs for each UART are ORed together. + */ + Object *orgate; + DeviceState *orgate_dev; + int i; + + orgate = object_new(TYPE_OR_IRQ); + object_property_set_int(orgate, 10, "num-lines", &error_fatal); + object_property_set_bool(orgate, true, "realized", &error_fatal); + orgate_dev = DEVICE(orgate); + qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); + + for (i = 0; i < 5; i++) { + /* system irq numbers for the combined tx/rx for each UART */ + static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; + static const hwaddr uartbase[] = {0x40004000, 0x40005000, + 0x4002c000, 0x4002d000, + 0x4002e000}; + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; + Object *txrx_orgate; + DeviceState *txrx_orgate_dev; + + txrx_orgate = object_new(TYPE_OR_IRQ); + object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal); + object_property_set_bool(txrx_orgate, true, "realized", + &error_fatal); + txrx_orgate_dev = DEVICE(txrx_orgate); + qdev_connect_gpio_out(txrx_orgate_dev, 0, + qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); + cmsdk_apb_uart_create(uartbase[i], + qdev_get_gpio_in(txrx_orgate_dev, 0), + qdev_get_gpio_in(txrx_orgate_dev, 1), + qdev_get_gpio_in(orgate_dev, 0), + qdev_get_gpio_in(orgate_dev, 1), + NULL, + uartchr, SYSCLK_FRQ); + } + break; + } + default: + g_assert_not_reached(); + } + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c index ab34729..1ad1e14 100644 --- a/hw/char/cmsdk-apb-uart.c +++ b/hw/char/cmsdk-apb-uart.c @@ -339,7 +339,7 @@ static void cmsdk_apb_uart_realize(DeviceState *dev, Error **errp) * an event handler to deal with CHR_EVENT_BREAK. */ qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, - NULL, s, NULL, true); + NULL, NULL, s, NULL, true); } static int cmsdk_apb_uart_post_load(void *opaque, int version_id)