From patchwork Mon Jul 17 12:44:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 107931 Delivered-To: patch@linaro.org Received: by 10.140.101.44 with SMTP id t41csp4480735qge; Mon, 17 Jul 2017 05:58:59 -0700 (PDT) X-Received: by 10.200.54.210 with SMTP id b18mr6355887qtc.145.1500296339351; Mon, 17 Jul 2017 05:58:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1500296339; cv=none; d=google.com; s=arc-20160816; b=IRrsB23uFW35Ub4gbbGcugQeuqBg3FvLuqlJzgPMDJXPr/V5xsEimAzc6xyGSoMoZO Lj2mVR60GsZAH7B5kKHJS0mmC1XCywzP58kZqCZQGTzqERMS9E9yimZBh791VQdv6Jt3 +wqBGUQ/mLIvDIt3pT21HZNXXgH1U7ZhpXZjYkDMsCXO6ONVgqYKmWNroMBPvKGJFt5S LeqSCHIU7P+AnScxfqEDmjCXug2bYLU2Ngt9FylMXWAPKr2tW96+/sSHqMO4mHNjZm1g e6VPnqyNyh8A0oIIdu93ORQ/B9yVeTWgyr3U5OKC6mmLdMsbUV+TIUS+snknYKGUlgBe 8ldA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=S6k8+rRJJRGBpw1Xi3R/0r2ThR/8/hJfdq8ai74CZnE=; b=VXnar4gD127yBUmBgn9/6Nf+jvmpkk10qzc5/YB+MQQWmU+iASJ7W60r9eTs2crbQt uhtEY4YcBzf0inTn2UFfAy94efGSdcdeevQe2mD4HWqNhOuUoUwWDQZ0CNA1UC9aJYBY Xm1PL+u8Gly/QU670dY70QdI75z1vVT5KUTGju6hSDopKyi7IQFmY8CDCC6cxDQIBsWx rsUPy1fgSuVbYAHX827wukOt9bc3CNqq9NuCRyu23E2VYA6HW6ZEoJ17epu+NQxOfNeF APDziUsHf5+DWrgaBsls6tBbboVvPeKh4Oj2FKGXbdx/5z63b6LHcwg0JfPdxlDB60EK iTxQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f62si14400792qkb.197.2017.07.17.05.58.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 17 Jul 2017 05:58:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50234 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dX5c1-0002EV-33 for patch@linaro.org; Mon, 17 Jul 2017 08:58:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dX5Oh-00080C-NV for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dX5Og-0002Ku-HT for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37640) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dX5Og-0002Ci-BY for qemu-devel@nongnu.org; Mon, 17 Jul 2017 08:45:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dX5OS-0003S8-LD for qemu-devel@nongnu.org; Mon, 17 Jul 2017 13:44:56 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jul 2017 13:44:39 +0100 Message-Id: <1500295494-8991-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500295494-8991-1-git-send-email-peter.maydell@linaro.org> References: <1500295494-8991-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/18] target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Cortex-M3 and M4 CPUs always have 8 PMSA MPU regions (this isn't a configurable option for the hardware). Make the default value of the pmsav7-dregion property be set per-cpu, so we don't need to have every user of these CPUs set it manually. (The existing default of 16 is correct for the other PMSAv7 core, the Cortex-R5.) This fixes a bug where we were creating the M3 and M4 with too many regions; most guest software would not notice or care, though, since it would just not use the registers associated with the unexpected extra regions. Signed-off-by: Peter Maydell Reviewed-by: Marc-André Lureau Message-id: 1499788408-10096-4-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 28a9141..96d1f84 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -543,8 +543,15 @@ static Property arm_cpu_has_pmu_property = static Property arm_cpu_has_mpu_property = DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); +/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, + * because the CPU initfn will have already set cpu->pmsav7_dregion to + * the right value for that particular CPU type, and we don't want + * to override that with an incorrect constant value. + */ static Property arm_cpu_pmsav7_dregion_property = - DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); + DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, + pmsav7_dregion, + qdev_prop_uint32, uint32_t); static void arm_cpu_post_init(Object *obj) { @@ -1054,6 +1061,7 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); cpu->midr = 0x410fc231; + cpu->pmsav7_dregion = 8; } static void cortex_m4_initfn(Object *obj) @@ -1064,6 +1072,7 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr = 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion = 8; } static void arm_v7m_class_init(ObjectClass *oc, void *data) { @@ -1112,6 +1121,7 @@ static void cortex_r5_initfn(Object *obj) cpu->id_isar4 = 0x0010142; cpu->id_isar5 = 0x0; cpu->mp_is_up = true; + cpu->pmsav7_dregion = 16; define_arm_cp_regs(cpu, cortexr5_cp_reginfo); }