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[207.126.144.143]) by mx.google.com with SMTP id 1si2320199eee.133.2012.08.22.01.44.13 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 22 Aug 2012 01:44:23 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.143 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.143; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.143 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob117.postini.com ([207.126.147.11]) with SMTP ID DSNKUDSb3dXGUYlbgN43iMvB3gmfL/Oq0E1q@postini.com; Wed, 22 Aug 2012 08:44:23 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id C825C4E; Wed, 22 Aug 2012 08:43:26 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id B4AE248; Wed, 22 Aug 2012 05:00:47 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 291F524C3FA; Wed, 22 Aug 2012 10:43:47 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 22 Aug 2012 10:43:52 +0200 From: Linus Walleij To: , , Samuel Ortiz Cc: Etienne Carriere , Linus Walleij Subject: [PATCH 1/7] ux500: GIC: MASK_ON_SUSPEND Date: Wed, 22 Aug 2012 10:43:48 +0200 Message-ID: <1345625028-5608-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlPr53YttSdqIlJyQnEuD3MDR8YPbTQ9FcWb08DdbkbB2/2hDVSX68tLn/U/lITmVGIdKpk From: Etienne Carriere ux500 machines performs pins (GPIO) reconfiguration when entering in the suspended mode. This reconfiguration aims at reaching an ultra low power HW configuration. Due to this HW reconfiguration, some HW devices can change of HW state and have their output signals at level that could generate IRQs. If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt disable feature from the generic irq layer), effective interrupts reach the system only because the system attempt to enter the suspended mode. To prevent such IRQs to trig, all irq chips embedded in ux500 platform should enable their IRQCHIP_MASK_ON_SUSPEND flag. Signed-off-by: Etienne Carriere Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index e2360e7..84d7f7e 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -51,6 +51,8 @@ void __init ux500_init_irq(void) void __iomem *dist_base; void __iomem *cpu_base; + gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; + if (cpu_is_u8500_family()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE);