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[207.126.144.113]) by mx.google.com with SMTP id j48si2324262eeo.114.2012.08.22.01.44.22 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 22 Aug 2012 01:44:30 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.113; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob102.postini.com ([207.126.147.11]) with SMTP ID DSNKUDSb5mMnxfB7kIVAzJ7UWCmg/aAMCkDF@postini.com; Wed, 22 Aug 2012 08:44:29 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4B20FE4; Wed, 22 Aug 2012 08:43:59 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id ED13826E9; Wed, 22 Aug 2012 08:43:58 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id C9B02A8065; Wed, 22 Aug 2012 10:43:54 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 22 Aug 2012 10:43:58 +0200 From: Linus Walleij To: , , Samuel Ortiz Cc: Etienne Carriere , Linus Walleij Subject: [PATCH 2/7] mfd/ab8500: MASK_ON_SUSPEND Date: Wed, 22 Aug 2012 10:43:56 +0200 Message-ID: <1345625036-5643-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnCIXKNeAmzyvC7jOZq+wcMx0rMVIEqdWvbDNXIFC4a13HQmhpP8MkYdrbaV/xD9EgzR6y2 From: Etienne Carriere ux500 machines performs pins (GPIO) reconfiguration when entering in the suspended mode. This reconfiguration aims at reaching an ultra low power HW configuration. Due to this HW reconfiguration, some HW devices can change of HW state and have their output signals at level that could generate IRQs. If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt disable feature from the generic irq layer), effective interrupts reach the system only because the system attempt to enter the suspended mode. To prevent such IRQs to trig, all irq chips embedded in ux500 platform should enable their IRQCHIP_MASK_ON_SUSPEND flag. Cc: Samuel Ortiz Signed-off-by: Etienne Carriere Signed-off-by: Linus Walleij --- drivers/mfd/ab8500-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c index 626b4ec..b25a0b0 100644 --- a/drivers/mfd/ab8500-core.c +++ b/drivers/mfd/ab8500-core.c @@ -386,6 +386,7 @@ static struct irq_chip ab8500_irq_chip = { .irq_mask = ab8500_irq_mask, .irq_disable = ab8500_irq_mask, .irq_unmask = ab8500_irq_unmask, + .flags = IRQCHIP_MASK_ON_SUSPEND, }; static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,