From patchwork Wed Aug 22 08:44:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 10862 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B9B7023E56 for ; Wed, 22 Aug 2012 08:44:44 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8F6C7A18603 for ; Wed, 22 Aug 2012 08:44:33 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id j38so642474iad.11 for ; Wed, 22 Aug 2012 01:44:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=BeNx9gJJ8g1hLZsM+An0Bw1qtAqDuBhbnQntD5aUAU4=; b=Nv10MeoW5KjSJx8s9NBjP/5RHVv6slWPWMaiJr5GHOsgfVNBshzY1+ThhCKar7DFel 5He4+oG5h0Yp3CDaVEdi/RSYARaLHjkLxbuokhjBbqyxTwqkErGmc5QyLE9Cl8V/1O6y i1GFjT/SsJOlkDcyyfaiMm5UzJzXNyqscbcpvgP5JZ/x1DA33A6ohOYdJujd+83Kh+cC AU7n4TeYNpYIPlgB4SjzcUm/A+WVO/IX1JCYAmkqQ8SZ1b36iTC/Vsf5VUG8lwO2SqkO l3ybVfX8CS89uuCiBrcc7SKqaZ16wWY7nZGW9KLfGBHHWaDYviDzYNjRTY+JPU3TyVPy mKGA== Received: by 10.50.207.106 with SMTP id lv10mr1365820igc.0.1345625084257; Wed, 22 Aug 2012 01:44:44 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp190159igc; Wed, 22 Aug 2012 01:44:43 -0700 (PDT) Received: by 10.14.204.200 with SMTP id h48mr17508418eeo.7.1345625083025; Wed, 22 Aug 2012 01:44:43 -0700 (PDT) Received: from eu1sys200aog113.obsmtp.com (eu1sys200aog113.obsmtp.com. [207.126.144.135]) by mx.google.com with SMTP id c41si2325293eem.110.2012.08.22.01.44.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 22 Aug 2012 01:44:43 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.135; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob113.postini.com ([207.126.147.11]) with SMTP ID DSNKUDSb8w7n5dP+fcxDFyLOmaQnNAA6oaGM@postini.com; Wed, 22 Aug 2012 08:44:42 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 68F71D1; Wed, 22 Aug 2012 08:44:34 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2548427BE; Wed, 22 Aug 2012 08:44:34 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id F1471A8065; Wed, 22 Aug 2012 10:44:29 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 22 Aug 2012 10:44:33 +0200 From: Linus Walleij To: , , Samuel Ortiz Cc: Etienne Carriere , Linus Walleij Subject: [PATCH 7/7] mfd/tc3589x: MASK_ON_SUSPEND Date: Wed, 22 Aug 2012 10:44:30 +0200 Message-ID: <1345625070-5820-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQn0Kf/3pIOb3Q6SRiG/xe6kYZK+jAUccgdqXtIOP1C4BD67KcMwrhiziSDzHOgRuyAU2RnT From: Etienne Carriere ux500 machines performs pins (GPIO) reconfiguration when entering in the suspended mode. This reconfiguration aims at reaching an ultra low power HW configuration. Due to this HW reconfiguration, some HW devices can change of HW state and have their output signals at level that could generate IRQs. If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt disable feature from the generic irq layer), effective interrupts reach the system only because the system attempt to enter the suspended mode. To prevent such IRQs to trig, all irq chips embedded in ux500 platform should enable their IRQCHIP_MASK_ON_SUSPEND flag. Cc: Samuel Ortiz Signed-off-by: Etienne Carriere Signed-off-by: Linus Walleij --- drivers/gpio/gpio-tc3589x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-tc3589x.c b/drivers/gpio/gpio-tc3589x.c index 2a82e89..6e48c50 100644 --- a/drivers/gpio/gpio-tc3589x.c +++ b/drivers/gpio/gpio-tc3589x.c @@ -199,6 +199,7 @@ static struct irq_chip tc3589x_gpio_irq_chip = { .irq_mask = tc3589x_gpio_irq_mask, .irq_unmask = tc3589x_gpio_irq_unmask, .irq_set_type = tc3589x_gpio_irq_set_type, + .flags = IRQCHIP_MASK_ON_SUSPEND, }; static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)