diff mbox series

[01/15] target/arm: Use MMUAccessType enum rather than int

Message ID 1501692241-23310-2-git-send-email-peter.maydell@linaro.org
State Accepted
Commit 03ae85f858fc46495258a5dd4551fff2c34bd495
Headers show
Series v7M: cleanups and bugfixes prior to v8M | expand

Commit Message

Peter Maydell Aug. 2, 2017, 4:43 p.m. UTC 
In the ARM get_phys_addr() code, switch to using the MMUAccessType
enum and its MMU_* values rather than int and literal 0/1/2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c    | 30 +++++++++++++++---------------
 target/arm/internals.h |  3 ++-
 2 files changed, 17 insertions(+), 16 deletions(-)

-- 
2.7.4

Comments

Edgar E. Iglesias Aug. 2, 2017, 5:27 p.m. UTC | #1 
On Wed, Aug 02, 2017 at 05:43:47PM +0100, Peter Maydell wrote:
> In the ARM get_phys_addr() code, switch to using the MMUAccessType

> enum and its MMU_* values rather than int and literal 0/1/2.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>



> ---

>  target/arm/helper.c    | 30 +++++++++++++++---------------

>  target/arm/internals.h |  3 ++-

>  2 files changed, 17 insertions(+), 16 deletions(-)

> 

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index fa60040..b78d277 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -20,13 +20,13 @@

>  

>  #ifndef CONFIG_USER_ONLY

>  static bool get_phys_addr(CPUARMState *env, target_ulong address,

> -                          int access_type, ARMMMUIdx mmu_idx,

> +                          MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                            hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

>                            target_ulong *page_size, uint32_t *fsr,

>                            ARMMMUFaultInfo *fi);

>  

>  static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

> -                               int access_type, ARMMMUIdx mmu_idx,

> +                               MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

>                                 target_ulong *page_size_ptr, uint32_t *fsr,

>                                 ARMMMUFaultInfo *fi);

> @@ -2135,7 +2135,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,

>  }

>  

>  static uint64_t do_ats_write(CPUARMState *env, uint64_t value,

> -                             int access_type, ARMMMUIdx mmu_idx)

> +                             MMUAccessType access_type, ARMMMUIdx mmu_idx)

>  {

>      hwaddr phys_addr;

>      target_ulong page_size;

> @@ -2194,7 +2194,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,

>  

>  static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>  {

> -    int access_type = ri->opc2 & 1;

> +    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

>      uint64_t par64;

>      ARMMMUIdx mmu_idx;

>      int el = arm_current_el(env);

> @@ -2253,7 +2253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>  static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,

>                          uint64_t value)

>  {

> -    int access_type = ri->opc2 & 1;

> +    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

>      uint64_t par64;

>  

>      par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);

> @@ -2273,7 +2273,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,

>  static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,

>                          uint64_t value)

>  {

> -    int access_type = ri->opc2 & 1;

> +    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

>      ARMMMUIdx mmu_idx;

>      int secure = arm_is_secure_below_el3(env);

>  

> @@ -7510,7 +7510,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,

>  }

>  

>  static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,

> -                             int access_type, ARMMMUIdx mmu_idx,

> +                             MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                               hwaddr *phys_ptr, int *prot,

>                               target_ulong *page_size, uint32_t *fsr,

>                               ARMMMUFaultInfo *fi)

> @@ -7626,7 +7626,7 @@ do_fault:

>  }

>  

>  static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,

> -                             int access_type, ARMMMUIdx mmu_idx,

> +                             MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                               hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

>                               target_ulong *page_size, uint32_t *fsr,

>                               ARMMMUFaultInfo *fi)

> @@ -7733,7 +7733,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,

>          if (pxn && !regime_is_user(env, mmu_idx)) {

>              xn = 1;

>          }

> -        if (xn && access_type == 2)

> +        if (xn && access_type == MMU_INST_FETCH)

>              goto do_fault;

>  

>          if (arm_feature(env, ARM_FEATURE_V6K) &&

> @@ -7848,7 +7848,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,

>  }

>  

>  static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

> -                               int access_type, ARMMMUIdx mmu_idx,

> +                               MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

>                                 target_ulong *page_size_ptr, uint32_t *fsr,

>                                 ARMMMUFaultInfo *fi)

> @@ -8256,7 +8256,7 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address)

>  }

>  

>  static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,

> -                                 int access_type, ARMMMUIdx mmu_idx,

> +                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                   hwaddr *phys_ptr, int *prot, uint32_t *fsr)

>  {

>      ARMCPU *cpu = arm_env_get_cpu(env);

> @@ -8415,7 +8415,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,

>  }

>  

>  static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

> -                                 int access_type, ARMMMUIdx mmu_idx,

> +                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                   hwaddr *phys_ptr, int *prot, uint32_t *fsr)

>  {

>      int n;

> @@ -8442,7 +8442,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

>          return true;

>      }

>  

> -    if (access_type == 2) {

> +    if (access_type == MMU_INST_FETCH) {

>          mask = env->cp15.pmsav5_insn_ap;

>      } else {

>          mask = env->cp15.pmsav5_data_ap;

> @@ -8513,7 +8513,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

>   * @fsr: set to the DFSR/IFSR value on failure

>   */

>  static bool get_phys_addr(CPUARMState *env, target_ulong address,

> -                          int access_type, ARMMMUIdx mmu_idx,

> +                          MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                            hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

>                            target_ulong *page_size, uint32_t *fsr,

>                            ARMMMUFaultInfo *fi)

> @@ -8626,7 +8626,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,

>   * fsr with ARM DFSR/IFSR fault register format value on failure.

>   */

>  bool arm_tlb_fill(CPUState *cs, vaddr address,

> -                  int access_type, int mmu_idx, uint32_t *fsr,

> +                  MMUAccessType access_type, int mmu_idx, uint32_t *fsr,

>                    ARMMMUFaultInfo *fi)

>  {

>      ARMCPU *cpu = ARM_CPU(cs);

> diff --git a/target/arm/internals.h b/target/arm/internals.h

> index 1f6efef..bb06946 100644

> --- a/target/arm/internals.h

> +++ b/target/arm/internals.h

> @@ -457,7 +457,8 @@ struct ARMMMUFaultInfo {

>  };

>  

>  /* Do a page table walk and add page to TLB if possible */

> -bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,

> +bool arm_tlb_fill(CPUState *cpu, vaddr address,

> +                  MMUAccessType access_type, int mmu_idx,

>                    uint32_t *fsr, ARMMMUFaultInfo *fi);

>  

>  /* Return true if the stage 1 translation regime is using LPAE format page

> -- 

> 2.7.4

> 

>
Philippe Mathieu-Daudé Aug. 2, 2017, 9:52 p.m. UTC | #2 
On 08/02/2017 01:43 PM, Peter Maydell wrote:
> In the ARM get_phys_addr() code, switch to using the MMUAccessType

> enum and its MMU_* values rather than int and literal 0/1/2.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


> ---

>   target/arm/helper.c    | 30 +++++++++++++++---------------

>   target/arm/internals.h |  3 ++-

>   2 files changed, 17 insertions(+), 16 deletions(-)

> 

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index fa60040..b78d277 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -20,13 +20,13 @@

>   

>   #ifndef CONFIG_USER_ONLY

>   static bool get_phys_addr(CPUARMState *env, target_ulong address,

> -                          int access_type, ARMMMUIdx mmu_idx,

> +                          MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                             hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

>                             target_ulong *page_size, uint32_t *fsr,

>                             ARMMMUFaultInfo *fi);

>   

>   static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

> -                               int access_type, ARMMMUIdx mmu_idx,

> +                               MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                  hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

>                                  target_ulong *page_size_ptr, uint32_t *fsr,

>                                  ARMMMUFaultInfo *fi);

> @@ -2135,7 +2135,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,

>   }

>   

>   static uint64_t do_ats_write(CPUARMState *env, uint64_t value,

> -                             int access_type, ARMMMUIdx mmu_idx)

> +                             MMUAccessType access_type, ARMMMUIdx mmu_idx)

>   {

>       hwaddr phys_addr;

>       target_ulong page_size;

> @@ -2194,7 +2194,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,

>   

>   static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>   {

> -    int access_type = ri->opc2 & 1;

> +    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

>       uint64_t par64;

>       ARMMMUIdx mmu_idx;

>       int el = arm_current_el(env);

> @@ -2253,7 +2253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)

>   static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,

>                           uint64_t value)

>   {

> -    int access_type = ri->opc2 & 1;

> +    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

>       uint64_t par64;

>   

>       par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);

> @@ -2273,7 +2273,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,

>   static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,

>                           uint64_t value)

>   {

> -    int access_type = ri->opc2 & 1;

> +    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;

>       ARMMMUIdx mmu_idx;

>       int secure = arm_is_secure_below_el3(env);

>   

> @@ -7510,7 +7510,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,

>   }

>   

>   static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,

> -                             int access_type, ARMMMUIdx mmu_idx,

> +                             MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                hwaddr *phys_ptr, int *prot,

>                                target_ulong *page_size, uint32_t *fsr,

>                                ARMMMUFaultInfo *fi)

> @@ -7626,7 +7626,7 @@ do_fault:

>   }

>   

>   static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,

> -                             int access_type, ARMMMUIdx mmu_idx,

> +                             MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

>                                target_ulong *page_size, uint32_t *fsr,

>                                ARMMMUFaultInfo *fi)

> @@ -7733,7 +7733,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,

>           if (pxn && !regime_is_user(env, mmu_idx)) {

>               xn = 1;

>           }

> -        if (xn && access_type == 2)

> +        if (xn && access_type == MMU_INST_FETCH)

>               goto do_fault;

>   

>           if (arm_feature(env, ARM_FEATURE_V6K) &&

> @@ -7848,7 +7848,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,

>   }

>   

>   static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

> -                               int access_type, ARMMMUIdx mmu_idx,

> +                               MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                  hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

>                                  target_ulong *page_size_ptr, uint32_t *fsr,

>                                  ARMMMUFaultInfo *fi)

> @@ -8256,7 +8256,7 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address)

>   }

>   

>   static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,

> -                                 int access_type, ARMMMUIdx mmu_idx,

> +                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                    hwaddr *phys_ptr, int *prot, uint32_t *fsr)

>   {

>       ARMCPU *cpu = arm_env_get_cpu(env);

> @@ -8415,7 +8415,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,

>   }

>   

>   static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

> -                                 int access_type, ARMMMUIdx mmu_idx,

> +                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                                    hwaddr *phys_ptr, int *prot, uint32_t *fsr)

>   {

>       int n;

> @@ -8442,7 +8442,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

>           return true;

>       }

>   

> -    if (access_type == 2) {

> +    if (access_type == MMU_INST_FETCH) {

>           mask = env->cp15.pmsav5_insn_ap;

>       } else {

>           mask = env->cp15.pmsav5_data_ap;

> @@ -8513,7 +8513,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,

>    * @fsr: set to the DFSR/IFSR value on failure

>    */

>   static bool get_phys_addr(CPUARMState *env, target_ulong address,

> -                          int access_type, ARMMMUIdx mmu_idx,

> +                          MMUAccessType access_type, ARMMMUIdx mmu_idx,

>                             hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

>                             target_ulong *page_size, uint32_t *fsr,

>                             ARMMMUFaultInfo *fi)

> @@ -8626,7 +8626,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,

>    * fsr with ARM DFSR/IFSR fault register format value on failure.

>    */

>   bool arm_tlb_fill(CPUState *cs, vaddr address,

> -                  int access_type, int mmu_idx, uint32_t *fsr,

> +                  MMUAccessType access_type, int mmu_idx, uint32_t *fsr,

>                     ARMMMUFaultInfo *fi)

>   {

>       ARMCPU *cpu = ARM_CPU(cs);

> diff --git a/target/arm/internals.h b/target/arm/internals.h

> index 1f6efef..bb06946 100644

> --- a/target/arm/internals.h

> +++ b/target/arm/internals.h

> @@ -457,7 +457,8 @@ struct ARMMMUFaultInfo {

>   };

>   

>   /* Do a page table walk and add page to TLB if possible */

> -bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,

> +bool arm_tlb_fill(CPUState *cpu, vaddr address,

> +                  MMUAccessType access_type, int mmu_idx,

>                     uint32_t *fsr, ARMMMUFaultInfo *fi);

>   

>   /* Return true if the stage 1 translation regime is using LPAE format page

>
Richard Henderson Aug. 3, 2017, 8:13 p.m. UTC | #3 
On 08/02/2017 09:43 AM, Peter Maydell wrote:
> In the ARM get_phys_addr() code, switch to using the MMUAccessType

> enum and its MMU_* values rather than int and literal 0/1/2.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/helper.c    | 30 +++++++++++++++---------------

>  target/arm/internals.h |  3 ++-

>  2 files changed, 17 insertions(+), 16 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index fa60040..b78d277 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -20,13 +20,13 @@ 
 
 #ifndef CONFIG_USER_ONLY
 static bool get_phys_addr(CPUARMState *env, target_ulong address,
-                          int access_type, ARMMMUIdx mmu_idx,
+                          MMUAccessType access_type, ARMMMUIdx mmu_idx,
                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
                           target_ulong *page_size, uint32_t *fsr,
                           ARMMMUFaultInfo *fi);
 
 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
-                               int access_type, ARMMMUIdx mmu_idx,
+                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
                                target_ulong *page_size_ptr, uint32_t *fsr,
                                ARMMMUFaultInfo *fi);
@@ -2135,7 +2135,7 @@  static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
-                             int access_type, ARMMMUIdx mmu_idx)
+                             MMUAccessType access_type, ARMMMUIdx mmu_idx)
 {
     hwaddr phys_addr;
     target_ulong page_size;
@@ -2194,7 +2194,7 @@  static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
 
 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 {
-    int access_type = ri->opc2 & 1;
+    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
     uint64_t par64;
     ARMMMUIdx mmu_idx;
     int el = arm_current_el(env);
@@ -2253,7 +2253,7 @@  static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
-    int access_type = ri->opc2 & 1;
+    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
     uint64_t par64;
 
     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
@@ -2273,7 +2273,7 @@  static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
-    int access_type = ri->opc2 & 1;
+    MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
     ARMMMUIdx mmu_idx;
     int secure = arm_is_secure_below_el3(env);
 
@@ -7510,7 +7510,7 @@  static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
 }
 
 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
-                             int access_type, ARMMMUIdx mmu_idx,
+                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
                              hwaddr *phys_ptr, int *prot,
                              target_ulong *page_size, uint32_t *fsr,
                              ARMMMUFaultInfo *fi)
@@ -7626,7 +7626,7 @@  do_fault:
 }
 
 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
-                             int access_type, ARMMMUIdx mmu_idx,
+                             MMUAccessType access_type, ARMMMUIdx mmu_idx,
                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
                              target_ulong *page_size, uint32_t *fsr,
                              ARMMMUFaultInfo *fi)
@@ -7733,7 +7733,7 @@  static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
         if (pxn && !regime_is_user(env, mmu_idx)) {
             xn = 1;
         }
-        if (xn && access_type == 2)
+        if (xn && access_type == MMU_INST_FETCH)
             goto do_fault;
 
         if (arm_feature(env, ARM_FEATURE_V6K) &&
@@ -7848,7 +7848,7 @@  static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
 }
 
 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
-                               int access_type, ARMMMUIdx mmu_idx,
+                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
                                target_ulong *page_size_ptr, uint32_t *fsr,
                                ARMMMUFaultInfo *fi)
@@ -8256,7 +8256,7 @@  static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
 }
 
 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
-                                 int access_type, ARMMMUIdx mmu_idx,
+                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,
                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
 {
     ARMCPU *cpu = arm_env_get_cpu(env);
@@ -8415,7 +8415,7 @@  static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
 }
 
 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
-                                 int access_type, ARMMMUIdx mmu_idx,
+                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,
                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
 {
     int n;
@@ -8442,7 +8442,7 @@  static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
         return true;
     }
 
-    if (access_type == 2) {
+    if (access_type == MMU_INST_FETCH) {
         mask = env->cp15.pmsav5_insn_ap;
     } else {
         mask = env->cp15.pmsav5_data_ap;
@@ -8513,7 +8513,7 @@  static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
  * @fsr: set to the DFSR/IFSR value on failure
  */
 static bool get_phys_addr(CPUARMState *env, target_ulong address,
-                          int access_type, ARMMMUIdx mmu_idx,
+                          MMUAccessType access_type, ARMMMUIdx mmu_idx,
                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
                           target_ulong *page_size, uint32_t *fsr,
                           ARMMMUFaultInfo *fi)
@@ -8626,7 +8626,7 @@  static bool get_phys_addr(CPUARMState *env, target_ulong address,
  * fsr with ARM DFSR/IFSR fault register format value on failure.
  */
 bool arm_tlb_fill(CPUState *cs, vaddr address,
-                  int access_type, int mmu_idx, uint32_t *fsr,
+                  MMUAccessType access_type, int mmu_idx, uint32_t *fsr,
                   ARMMMUFaultInfo *fi)
 {
     ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1f6efef..bb06946 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -457,7 +457,8 @@  struct ARMMMUFaultInfo {
 };
 
 /* Do a page table walk and add page to TLB if possible */
-bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
+bool arm_tlb_fill(CPUState *cpu, vaddr address,
+                  MMUAccessType access_type, int mmu_idx,
                   uint32_t *fsr, ARMMMUFaultInfo *fi);
 
 /* Return true if the stage 1 translation regime is using LPAE format page