| Message ID | 20170807145156.7880-1-guodong.xu@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 08/07, Guodong Xu wrote: > From: Zhong Kaihua <zhongkaihua@huawei.com> > > UART3 clock rate is doubled in previous commit. > > This error is not detected until recently a mezzanine board which makes > real use of uart3 port (through LS connector of 96boards) was setup > and tested on hi3660-hikey960 board. > > This patch changes clock source rate of clk_factor_uart3 to 100000000. > > Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> > Signed-off-by: Guodong Xu <guodong.xu@linaro.org> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index a18258e..f404199 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { /* crgctrl */ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { - { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, }, + { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, }, { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, }, { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, }, { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },