[v3,3/3] arm64: dts: qcom: Specify dload address for msm8916 and msm8996

Message ID 20170809201033.4967-4-bjorn.andersson@linaro.org
State Superseded
Headers show
Series
  • QCOM SCM Download mode support
Related show

Commit Message

Bjorn Andersson Aug. 9, 2017, 8:10 p.m.
On msm8916 and msm8996 boards a secure io-write is used to write the
magic for selecting "download mode", specify this address in the
DeviceTree.

Note that qcom_scm.download_mode=1 must be specified on the kernel
command line for the kernel to attempt selecting download mode.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 +++++++
 2 files changed, 9 insertions(+)

-- 
2.12.0

Comments

Bjorn Andersson Aug. 14, 2017, 9:58 p.m. | #1
On Wed 09 Aug 14:50 PDT 2017, Stephen Boyd wrote:

> On 08/09/2017 01:10 PM, Bjorn Andersson wrote:

> > On msm8916 and msm8996 boards a secure io-write is used to write the

> > magic for selecting "download mode", specify this address in the

> > DeviceTree.

> >

> > Note that qcom_scm.download_mode=1 must be specified on the kernel

> > command line for the kernel to attempt selecting download mode.

> >

> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> > ---

> >  arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++

> >  arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 +++++++

> >  2 files changed, 9 insertions(+)

> >

> > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi

> > index 039991f80831..b7197f2e7209 100644

> > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi

> > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi

> > @@ -241,6 +241,8 @@

> >  			clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;

> >  			clock-names = "core", "bus", "iface";

> >  			#reset-cells = <1>;

> > +

> > +			qcom,dload-mode = <&tcsr>;

> >  		};

> >  	};

> >  

> > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi

> > index 8f085716e258..2eee6a33f22b 100644

> > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi

> > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi

> > @@ -261,6 +261,8 @@

> >  	firmware {

> >  		scm {

> >  			compatible = "qcom,scm-msm8996";

> > +

> > +			qcom,dload-mode = <&tcsr>;

> 

> We don't need an offset into tcsr?

> 


Of course we do, this only worked with my previous (and incorrect) tcsr
definition - not the one I ended up including in the patch.

Thanks,
Bjorn

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 039991f80831..b7197f2e7209 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -241,6 +241,8 @@ 
 			clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 			clock-names = "core", "bus", "iface";
 			#reset-cells = <1>;
+
+			qcom,dload-mode = <&tcsr>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 8f085716e258..2eee6a33f22b 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -261,6 +261,8 @@ 
 	firmware {
 		scm {
 			compatible = "qcom,scm-msm8996";
+
+			qcom,dload-mode = <&tcsr>;
 		};
 	};
 
@@ -287,6 +289,11 @@ 
 			reg = <0x740000 0x20000>;
 		};
 
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-msm8996", "syscon";
+			reg = <0x7a0000 0x18000>;
+		};
+
 		intc: interrupt-controller@9bc0000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;