From patchwork Mon Aug 21 16:02:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110564 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4242580obb; Mon, 21 Aug 2017 09:03:28 -0700 (PDT) X-Received: by 10.99.133.65 with SMTP id u62mr16468924pgd.100.1503331408355; Mon, 21 Aug 2017 09:03:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331408; cv=none; d=google.com; s=arc-20160816; b=h38kkXy+28Hmp7hYl47b69lksQcl6HmwHUV2iBjImt4plqqVbfT8uSaSMkezt1MetP uim9CIHNARD4zp8SIUsk3hiFHSI1aRv+2cyDf/pCfpYc0SvX6/xM61h6MV3BS5ZJsg9C 9jMMQBDWy49N3RpcBtOcnwgI9HyJ8+UKNI+HXXAMw+f7YB9WbzpN9x+WFG+4S+1OwpSM dtsPq9jWVfPaRQ7o/ysUOgkgQRF/wtW4HhDChMybOFiiGT9CTO8eUOftgeZs+3s9b+7s P/g5lvNm0h3BlFsrQpA92xq2cPJrQy0QFGbMPNB2Nq5fa6+BFOb3xPsgS8rmnytLPpPD 4Ybg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=TLlHD9sSl/Lfv+/UZCVll5axMv4dEe/NlaLvxPjRM0k=; b=vn5pbajU+NdeGE9YpbKLIBT/SfZeZPYMGyZVHlHqowvRXKks1o7pMircrhFV1MsbwT U35qzWJQJZBOxbPPCll/G81gTirSC/gLEF0l2z6UAAVs8KCRZVQsHzq/ThjPVdJ/L/VJ w6GLpNEZ1rsBZWzeLOCeOO0Fd2tjhk0wG769aGJYsLvm3wuVMv0D935ie7wKo133NqOg 2zXpkPxT5Cr6Q9Mx4OyE99lDxeZh5bm6vKZtn72o9Gb49nr7ndDCaCrjlKi5blwgPj74 aXV6svjLX+NxgCdigSU0T84agyJYN2kbSf8Xq03DFpKUgLurgClQA8rSCm1q0rV1/hX5 nPXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=hegMe4qd; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b19si7567379pfh.86.2017.08.21.09.03.28; Mon, 21 Aug 2017 09:03:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=hegMe4qd; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754499AbdHUQDZ (ORCPT + 6 others); Mon, 21 Aug 2017 12:03:25 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:37480 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754454AbdHUQDR (ORCPT ); Mon, 21 Aug 2017 12:03:17 -0400 Received: by mail-wr0-f169.google.com with SMTP id z91so101575557wrc.4 for ; Mon, 21 Aug 2017 09:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DNSoQjIsa7AEBBP0HwX0AdrS4mGgMCPVhLtHMVbz0Ng=; b=hegMe4qdTA+IbI+SsXB4G/n42nL+yDmAmXEGFi2LaLR4z51RiJkCJQIOsoEiRIpdX5 2JdV15kp9yzqN1IgoGZ9+AphwWdBq4niiXO6dpMHuupdOoAXWQ7B7Y2t2NXNy/RpwHjF Gc+1kSGf8P5r5fMEBemE4H0Ayz1WT40Q80kaESgP8AKh7idZOFbeKTF1ga5fyCaA1fhb c5Vrzc/w/w/OvtjHm8xNAUVOPOiM3TLA7s8xANZwxLJSFD10tfZuSZAW9VpMFc3aep9A L3Ai8m5cHCRejZhWDEZr4hsZ6gv5lg1R2KaP8Y6N83AauU5W68IvhH/jg/DQCtU7rMSE 9fxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DNSoQjIsa7AEBBP0HwX0AdrS4mGgMCPVhLtHMVbz0Ng=; b=CvutgFN4Do991XBnyXc3uU5ETUDr0NxS4cXgZ8jYOpV7lhxT8UhUnrk/dcmqfPLSK1 ZXVH60TvVR4oczb5jOlWUQAnLpGY2adfCCBvIvsrK0rOYSk5YH0h8h8BApkkHl5T2S7e ITsTo557RYgKUKIujtqxzzLNXjxn8BZ1VgsVe2fLjd6vC+fpP5qlLz96M9V/PlXII9gi jCcm5z/pkD59pwA3Pc9Whamv/TwnyVT05ub9jGHHuMA0fsZE8vzY2KqpW+Y1QB6y6CHi MEHNOzK7AhBXDMPil6YH8BN1MDTyr5E9PzjUsqcr9wzDfIxbflkD3yxVyA8uNnr8assx dgKw== X-Gm-Message-State: AHYfb5hAp0laNA7QZJ98zk6Nt1vxnBjN0lMWKks7u+aHpEN/kv9g057j M9Psz92HPsu7rRSNDlU= X-Received: by 10.28.9.72 with SMTP id 69mr2277345wmj.154.1503331396449; Mon, 21 Aug 2017 09:03:16 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:15 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/16] mmc: meson-gx: work around clk-stop issue Date: Mon, 21 Aug 2017 18:02:55 +0200 Message-Id: <20170821160301.21899-11-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org It seems that the mmc clock is also used and required, somehow, by the controller it self. It is shown during init, when writing to CFG while the divider is set to 0 will crash the SoC. During voltage switch, the controller may crash and the card may then fail to exit busy state if the clock is stopped. To avoid this, it is best to keep the clock running for the controller, except during rate change. However, we still need to be able to gate the clock out of the SoC. Let's use the pinmux for this, and fallback to gpio mode (pulled-down) when we need to gate the clock Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 74 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 6 deletions(-) -- 2.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 0d3416dae8cf..c37e31dc709e 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -137,6 +137,10 @@ struct meson_host { struct clk *mmc_clk; unsigned long req_rate; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_clk_gate; + unsigned int bounce_buf_size; void *bounce_buf; dma_addr_t bounce_dma_addr; @@ -272,6 +276,42 @@ static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) return false; } +/* + * Gating the clock on this controller is tricky. It seems the mmc clock + * is also used by the controller. It may crash during some operation if the + * clock is stopped. The safest thing to do, whenever possible, is to keep + * clock running at stop it at the pad using the pinmux. + */ +static void meson_mmc_clk_gate(struct meson_host *host) +{ + u32 cfg; + + if (host->pins_clk_gate) { + pinctrl_select_state(host->pinctrl, host->pins_clk_gate); + } else { + /* + * If the pinmux is not provided - default to the classic and + * unsafe method + */ + cfg = readl(host->regs + SD_EMMC_CFG); + cfg |= CFG_STOP_CLOCK; + writel(cfg, host->regs + SD_EMMC_CFG); + } +} + +static void meson_mmc_clk_ungate(struct meson_host *host) +{ + u32 cfg; + + if (host->pins_clk_gate) + pinctrl_select_state(host->pinctrl, host->pins_default); + + /* Make sure the clock is not stopped in the controller */ + cfg = readl(host->regs + SD_EMMC_CFG); + cfg &= ~CFG_STOP_CLOCK; + writel(cfg, host->regs + SD_EMMC_CFG); +} + static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) { struct mmc_host *mmc = host->mmc; @@ -288,9 +328,7 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; /* stop clock */ - cfg = readl(host->regs + SD_EMMC_CFG); - cfg |= CFG_STOP_CLOCK; - writel(cfg, host->regs + SD_EMMC_CFG); + meson_mmc_clk_gate(host); host->req_rate = 0; if (!rate) { @@ -299,6 +337,11 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; } + /* Stop the clock during rate change to avoid glitches */ + cfg = readl(host->regs + SD_EMMC_CFG); + cfg |= CFG_STOP_CLOCK; + writel(cfg, host->regs + SD_EMMC_CFG); + ret = clk_set_rate(host->mmc_clk, rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", @@ -318,9 +361,7 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) dev_dbg(host->dev, "requested rate was %u\n", ios->clock); /* (re)start clock */ - cfg = readl(host->regs + SD_EMMC_CFG); - cfg &= ~CFG_STOP_CLOCK; - writel(cfg, host->regs + SD_EMMC_CFG); + meson_mmc_clk_ungate(host); return 0; } @@ -932,6 +973,27 @@ static int meson_mmc_probe(struct platform_device *pdev) goto free_host; } + host->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(host->pinctrl)) { + ret = PTR_ERR(host->pinctrl); + goto free_host; + } + + host->pins_default = pinctrl_lookup_state(host->pinctrl, + PINCTRL_STATE_DEFAULT); + if (IS_ERR(host->pins_default)) { + ret = PTR_ERR(host->pins_default); + goto free_host; + } + + host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, + "clk-gate"); + if (IS_ERR(host->pins_clk_gate)) { + dev_warn(&pdev->dev, + "can't get clk-gate pinctrl, using clk_stop bit\n"); + host->pins_clk_gate = NULL; + } + host->core_clk = devm_clk_get(&pdev->dev, "core"); if (IS_ERR(host->core_clk)) { ret = PTR_ERR(host->core_clk);