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[209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.50; Mon, 21 Aug 2017 16:48:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=JJWFSBfT; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754071AbdHUXst (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:49 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45835 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753548AbdHUXss (ORCPT ); Mon, 21 Aug 2017 19:48:48 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmLUU028087; Mon, 21 Aug 2017 18:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=tXp2X2zj9YbMjp9JcdHQP0KpHK6pfel1R/xnn5bWonI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JJWFSBfTAN4ZzmtIhpGwo74JrC+VFGtu+WdPjYicIULs69SeNJ3Aocqv+Ngls1RiL KQoDH8ZzPiRi/Pc/U8lkihmdWlZZAUAsYlWdZeiUN+AgkP3ErNRT60ycStuw+VK6M7 2A/zQpsLOGKtlTJdbnaBjm821j8mnyXqamvE+iFU= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLP1002312; Mon, 21 Aug 2017 18:48:21 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLOK025309; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307097; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 5/8] ARM: OMAP4: hwmod_data: Remove modulemode from IPU/DSP hwmods Date: Mon, 21 Aug 2017 18:48:15 -0500 Message-ID: <20170821234818.4755-6-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The .modulemode field is removed from both the IPU and DSP processor hwmods. This fixes a potential kernel crash during the shutdown sequence of any of these remoteproc devices, either during a normal teardown or during a recovery. The DSP and IPU processor subsystems are represented by multiple hwmods, one for each of the MMUs present within the subsystem and one for the processor cores. The processor subsystem is clocked from a single clock source with separate reset lines for each of the processors and the MMUs. This clock and reset information is represented in separate hwmods to allow the management of these entities in different drivers operating on the corresponding platform devices. This doesn't fit quite well into the current omap_hwmod layer due to these inter-dependencies. A remoteproc startup sequence involves enabling and programming of the MMUs, loading of the firmware into RAM mapped by the MMUs, and releasing the processors from reset. A shutdown sequence follows a reverse pattern with the processors put into reset first followed by the unmapping and disabling of the MMUs. Both the processors and the MMUs are present within a single clock domain and requires the domain be clocked and enabled until the last entity. The kernel crash can happen during the unmapping phase of the MMUs, as the hwmod layer disables the module during the omap_device_idle processing of the processor hwmod. This issue is fixed by not defining a modulemode for the IPU/DSP processors, which results in keeping the module in an activated state. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 -- 1 file changed, 2 deletions(-) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 3e2d792fd9df..d183ffdf37e6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -550,7 +550,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, }; @@ -1561,7 +1560,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, };