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[209.132.180.131]) by mx.google.com with ESMTPS id z1si8352090plh.999.2017.08.22.02.23.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Aug 2017 02:23:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-460691-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=m30/Z0HN; spf=pass (google.com: domain of gcc-patches-return-460691-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-460691-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=ncBaQou//ilvoHaNzoTJ74HFLcjzYglyyy87dAG+4i7jhtz2W8hI1 lWsoIc2zQawV9id4sheHP12rVLqsbQwzp0D7aeiGSa1m+YjbyM7b31pYtOMYKbCD Mroao4hso/1RzE47USIUdq5wK+grjMThBLTUzzXn+JWUbXUBiIWf0I= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=WhJpnv8Z6ECpXp0f5YYqYekBl6Y=; b=m30/Z0HNZvEjhV4m5SI0 ctzzS7QWIJ3jd5AzdzE8Lh+QcdgFQDYCBS/aSU++NN21maJNac4xneXfi7xgoD+B pG5ROJFQMm3zAha20yjG0Z3WeNnSt/nhHPEfDlPQduvujQN6oiPHM7lDI1/cr2+K kO5TM2jYYZ3R7zLzbaGQLKs= Received: (qmail 108597 invoked by alias); 22 Aug 2017 09:22:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 108442 invoked by uid 89); 22 Aug 2017 09:22:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=eq, wydz, EQ, inverting X-HELO: mail-wr0-f179.google.com Received: from mail-wr0-f179.google.com (HELO mail-wr0-f179.google.com) (209.85.128.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 22 Aug 2017 09:22:42 +0000 Received: by mail-wr0-f179.google.com with SMTP id p14so51187652wrg.1 for ; Tue, 22 Aug 2017 02:22:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:date:message-id :user-agent:mime-version; bh=wP7bdlWESmvwevCkPN3k7WWEnSV0V0P52Aqm+cYIyQ4=; b=mYrSEyoAqO3IWAHKboMFHRghHAAcZNXvQJ7oD/1W5zVVHReH0E3pre0Aqt7Ybd7D3A HDVzm9bab0dArjjZ3btm7IiCbMAfrOsrssSqK5hSaZGoupUteAR4QTTaTb50koLhlDRb hNPpy7+yZbUGRH2GlnKlyz2k1d1wXANTGTO/Nbc7gDfhAf3gMIAxVkpoaG2Qy5RXwg0i qZ2CQm91EiRG3yP/sLGsFPh3nXSEMTlygxdcYFK4Pfc0DdF4SK2ABlXf2Xy4ciIKV2RV jAcF35xmpck4zTELBzGedwnF8eogqIMcX3Fe83/KOqZ/CZZB5QkM23FgnLtgjYYutTTP Ie3Q== X-Gm-Message-State: AHYfb5jpYDLT7URCDYpjZulk6h/ZVL/lPALhcA4pn02tq9t7Mf43ez8L drboZX2n0l7LaXLBA+pcag== X-Received: by 10.28.66.18 with SMTP id p18mr26183wma.60.1503393759545; Tue, 22 Aug 2017 02:22:39 -0700 (PDT) Received: from localhost ([95.145.139.63]) by smtp.gmail.com with ESMTPSA id b15sm10109596wrb.95.2017.08.22.02.22.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 02:22:38 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [AArch64] Rename cmp_result iterator Date: Tue, 22 Aug 2017 10:22:37 +0100 Message-ID: <87a82sc5ya.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 The comparison results provided by the V_cmp_result/v_cmp_result attribute were simply the corresponding integer vector. We'd also like to have easy access to the integer vector for SVE, but using "cmp_result" would be confusing because SVE comparisons return predicates instead of vectors. This patch therefore renames the attributes to the more general V_INT_EQUIV/v_int_equiv instead. As to the capitalisation: there are already many iterators that use all lowercase vs. all uppercase names to distinguish all lowercase vs. all uppercase expansions (e.g. fcvt_target and FCVT_TARGET). It's also the convention used for the built-in mode/MODE/code/CODE/etc. attributes. IMO those names are easier to read at a glance, rather than relying on a single letter's difference. Tested on aarch64-linux-gnu. OK to install? Richard 2017-08-22 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/iterators.md (V_cmp_result): Rename to... (V_INT_EQUIV): ...this. (v_cmp_result): Rename to... (v_int_equiv): ...this. * config/aarch64/aarch64.md (xorsign3): Update accordingly. * config/aarch64/aarch64-simd.md (xorsign3): Likewise. (copysign3): Likewise. (aarch64_simd_bsl_internal): Likewise. (aarch64_simd_bsl): Likewise. (vec_cmp): Likewise. (vcond): Likewise. (vcond): Likewise. (vcondu): Likewise. (aarch64_cm): Likewise. (aarch64_cmtst): Likewise. (aarch64_fac): Likewise. (vec_perm_const): Likewise. (vcond_mask_): Rename to... (vcond_mask_): ...this. (vec_cmp): Rename to... (vec_cmp): ...this. Index: gcc/config/aarch64/iterators.md =================================================================== --- gcc/config/aarch64/iterators.md 2017-08-22 10:11:04.727125997 +0100 +++ gcc/config/aarch64/iterators.md 2017-08-22 10:11:45.067177420 +0100 @@ -662,25 +662,25 @@ (define_mode_attr vwcore [(V8QI "w") (V ;; Double vector types for ALLX. (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) -;; Mode of result of comparison operations. -(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") - (V4HI "V4HI") (V8HI "V8HI") - (V2SI "V2SI") (V4SI "V4SI") - (DI "DI") (V2DI "V2DI") - (V4HF "V4HI") (V8HF "V8HI") - (V2SF "V2SI") (V4SF "V4SI") - (V2DF "V2DI") (DF "DI") - (SF "SI") (HF "HI")]) +;; Mode with floating-point values replaced by like-sized integers. +(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI") + (V4HI "V4HI") (V8HI "V8HI") + (V2SI "V2SI") (V4SI "V4SI") + (DI "DI") (V2DI "V2DI") + (V4HF "V4HI") (V8HF "V8HI") + (V2SF "V2SI") (V4SF "V4SI") + (V2DF "V2DI") (DF "DI") + (SF "SI") (HF "HI")]) -;; Lower case mode of results of comparison operations. -(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") - (V4HI "v4hi") (V8HI "v8hi") - (V2SI "v2si") (V4SI "v4si") - (DI "di") (V2DI "v2di") - (V4HF "v4hi") (V8HF "v8hi") - (V2SF "v2si") (V4SF "v4si") - (V2DF "v2di") (DF "di") - (SF "si")]) +;; Lower case mode with floating-point values replaced by like-sized integers. +(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi") + (V4HI "v4hi") (V8HI "v8hi") + (V2SI "v2si") (V4SI "v4si") + (DI "di") (V2DI "v2di") + (V4HF "v4hi") (V8HF "v8hi") + (V2SF "v2si") (V4SF "v4si") + (V2DF "v2di") (DF "di") + (SF "si")]) ;; Mode for vector conditional operations where the comparison has ;; different type from the lhs. Index: gcc/config/aarch64/aarch64.md =================================================================== --- gcc/config/aarch64/aarch64.md 2017-08-22 10:11:04.726102783 +0100 +++ gcc/config/aarch64/aarch64.md 2017-08-22 10:11:45.067177420 +0100 @@ -5196,7 +5196,7 @@ (define_expand "xorsign3" "TARGET_FLOAT && TARGET_SIMD" { - machine_mode imode = mode; + machine_mode imode = mode; rtx mask = gen_reg_rtx (imode); rtx op1x = gen_reg_rtx (imode); rtx op2x = gen_reg_rtx (imode); @@ -5205,13 +5205,13 @@ (define_expand "xorsign3" emit_move_insn (mask, GEN_INT (trunc_int_for_mode (HOST_WIDE_INT_M1U << bits, imode))); - emit_insn (gen_and3 (op2x, mask, - lowpart_subreg (imode, operands[2], - mode))); - emit_insn (gen_xor3 (op1x, - lowpart_subreg (imode, operands[1], - mode), - op2x)); + emit_insn (gen_and3 (op2x, mask, + lowpart_subreg (imode, operands[2], + mode))); + emit_insn (gen_xor3 (op1x, + lowpart_subreg (imode, operands[1], + mode), + op2x)); emit_move_insn (operands[0], lowpart_subreg (mode, op1x, imode)); DONE; Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-08-22 10:11:04.726102783 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2017-08-22 10:11:45.066232915 +0100 @@ -364,7 +364,7 @@ (define_expand "xorsign3" "TARGET_SIMD" { - machine_mode imode = mode; + machine_mode imode = mode; rtx v_bitmask = gen_reg_rtx (imode); rtx op1x = gen_reg_rtx (imode); rtx op2x = gen_reg_rtx (imode); @@ -375,11 +375,11 @@ (define_expand "xorsign3" int bits = GET_MODE_UNIT_BITSIZE (mode) - 1; emit_move_insn (v_bitmask, - aarch64_simd_gen_const_vector_dup (mode, + aarch64_simd_gen_const_vector_dup (mode, HOST_WIDE_INT_M1U << bits)); - emit_insn (gen_and3 (op2x, v_bitmask, arg2)); - emit_insn (gen_xor3 (op1x, arg1, op2x)); + emit_insn (gen_and3 (op2x, v_bitmask, arg2)); + emit_insn (gen_xor3 (op1x, arg1, op2x)); emit_move_insn (operands[0], lowpart_subreg (mode, op1x, imode)); DONE; @@ -392,11 +392,11 @@ (define_expand "copysign3" (match_operand:VHSDF 2 "register_operand")] "TARGET_FLOAT && TARGET_SIMD" { - rtx v_bitmask = gen_reg_rtx (mode); + rtx v_bitmask = gen_reg_rtx (mode); int bits = GET_MODE_UNIT_BITSIZE (mode) - 1; emit_move_insn (v_bitmask, - aarch64_simd_gen_const_vector_dup (mode, + aarch64_simd_gen_const_vector_dup (mode, HOST_WIDE_INT_M1U << bits)); emit_insn (gen_aarch64_simd_bsl (operands[0], v_bitmask, operands[2], operands[1])); @@ -2319,10 +2319,10 @@ (define_insn "aarch64_simd_bsl_int (xor:VSDQ_I_DI (and:VSDQ_I_DI (xor:VSDQ_I_DI - (match_operand: 3 "register_operand" "w,0,w") + (match_operand: 3 "register_operand" "w,0,w") (match_operand:VSDQ_I_DI 2 "register_operand" "w,w,0")) (match_operand:VSDQ_I_DI 1 "register_operand" "0,w,w")) - (match_dup: 3) + (match_dup: 3) ))] "TARGET_SIMD" "@ @@ -2357,7 +2357,7 @@ (define_insn "*aarch64_simd_bsl_al (define_expand "aarch64_simd_bsl" [(match_operand:VALLDIF 0 "register_operand") - (match_operand: 1 "register_operand") + (match_operand: 1 "register_operand") (match_operand:VALLDIF 2 "register_operand") (match_operand:VALLDIF 3 "register_operand")] "TARGET_SIMD" @@ -2366,26 +2366,26 @@ (define_expand "aarch64_simd_bsl" rtx tmp = operands[0]; if (FLOAT_MODE_P (mode)) { - operands[2] = gen_lowpart (mode, operands[2]); - operands[3] = gen_lowpart (mode, operands[3]); - tmp = gen_reg_rtx (mode); + operands[2] = gen_lowpart (mode, operands[2]); + operands[3] = gen_lowpart (mode, operands[3]); + tmp = gen_reg_rtx (mode); } - operands[1] = gen_lowpart (mode, operands[1]); - emit_insn (gen_aarch64_simd_bsl_internal (tmp, - operands[1], - operands[2], - operands[3])); + operands[1] = gen_lowpart (mode, operands[1]); + emit_insn (gen_aarch64_simd_bsl_internal (tmp, + operands[1], + operands[2], + operands[3])); if (tmp != operands[0]) emit_move_insn (operands[0], gen_lowpart (mode, tmp)); DONE; }) -(define_expand "vcond_mask_" +(define_expand "vcond_mask_" [(match_operand:VALLDI 0 "register_operand") (match_operand:VALLDI 1 "nonmemory_operand") (match_operand:VALLDI 2 "nonmemory_operand") - (match_operand: 3 "register_operand")] + (match_operand: 3 "register_operand")] "TARGET_SIMD" { /* If we have (a = (P) ? -1 : 0); @@ -2396,7 +2396,7 @@ (define_expand "vcond_mask_mode) && operands[2] == CONSTM1_RTX (mode)) - emit_insn (gen_one_cmpl2 (operands[0], operands[3])); + emit_insn (gen_one_cmpl2 (operands[0], operands[3])); else { if (!REG_P (operands[1])) @@ -2478,7 +2478,7 @@ (define_expand "vec_cmp" case NE: /* Handle NE as !EQ. */ emit_insn (gen_aarch64_cmeq (mask, operands[2], operands[3])); - emit_insn (gen_one_cmpl2 (mask, mask)); + emit_insn (gen_one_cmpl2 (mask, mask)); break; case EQ: @@ -2492,8 +2492,8 @@ (define_expand "vec_cmp" DONE; }) -(define_expand "vec_cmp" - [(set (match_operand: 0 "register_operand") +(define_expand "vec_cmp" + [(set (match_operand: 0 "register_operand") (match_operator 1 "comparison_operator" [(match_operand:VDQF 2 "register_operand") (match_operand:VDQF 3 "nonmemory_operand")]))] @@ -2501,7 +2501,7 @@ (define_expand "vec_cmpmode); + rtx tmp = gen_reg_rtx (mode); rtx (*comparison) (rtx, rtx, rtx) = NULL; @@ -2587,7 +2587,7 @@ (define_expand "vec_cmp !(a EQ b) */ gcc_assert (comparison != NULL); emit_insn (comparison (operands[0], operands[2], operands[3])); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); + emit_insn (gen_one_cmpl2 (operands[0], operands[0])); break; case LT: @@ -2612,8 +2612,8 @@ (define_expand "vec_cmp (operands[0], operands[2], operands[3])); emit_insn (gen_aarch64_cmgt (tmp, operands[3], operands[2])); - emit_insn (gen_ior3 (operands[0], operands[0], tmp)); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); + emit_insn (gen_ior3 (operands[0], operands[0], tmp)); + emit_insn (gen_one_cmpl2 (operands[0], operands[0])); break; case UNORDERED: @@ -2622,15 +2622,15 @@ (define_expand "vec_cmp (tmp, operands[2], operands[3])); emit_insn (gen_aarch64_cmge (operands[0], operands[3], operands[2])); - emit_insn (gen_ior3 (operands[0], operands[0], tmp)); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); + emit_insn (gen_ior3 (operands[0], operands[0], tmp)); + emit_insn (gen_one_cmpl2 (operands[0], operands[0])); break; case ORDERED: emit_insn (gen_aarch64_cmgt (tmp, operands[2], operands[3])); emit_insn (gen_aarch64_cmge (operands[0], operands[3], operands[2])); - emit_insn (gen_ior3 (operands[0], operands[0], tmp)); + emit_insn (gen_ior3 (operands[0], operands[0], tmp)); break; default: @@ -2662,7 +2662,7 @@ (define_expand "vcond" (match_operand:VALLDI 2 "nonmemory_operand")))] "TARGET_SIMD" { - rtx mask = gen_reg_rtx (mode); + rtx mask = gen_reg_rtx (mode); enum rtx_code code = GET_CODE (operands[3]); /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert @@ -2674,10 +2674,10 @@ (define_expand "vcond" operands[4], operands[5]); std::swap (operands[1], operands[2]); } - emit_insn (gen_vec_cmp (mask, operands[3], - operands[4], operands[5])); - emit_insn (gen_vcond_mask_ (operands[0], operands[1], - operands[2], mask)); + emit_insn (gen_vec_cmp (mask, operands[3], + operands[4], operands[5])); + emit_insn (gen_vcond_mask_ (operands[0], operands[1], + operands[2], mask)); DONE; }) @@ -2692,7 +2692,7 @@ (define_expand "vcond (match_operand: 2 "nonmemory_operand")))] "TARGET_SIMD" { - rtx mask = gen_reg_rtx (mode); + rtx mask = gen_reg_rtx (mode); enum rtx_code code = GET_CODE (operands[3]); /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert @@ -2704,9 +2704,9 @@ (define_expand "vcond operands[4], operands[5]); std::swap (operands[1], operands[2]); } - emit_insn (gen_vec_cmp (mask, operands[3], - operands[4], operands[5])); - emit_insn (gen_vcond_mask_ ( + emit_insn (gen_vec_cmp (mask, operands[3], + operands[4], operands[5])); + emit_insn (gen_vcond_mask_ ( operands[0], operands[1], operands[2], mask)); @@ -2737,8 +2737,8 @@ (define_expand "vcondu" } emit_insn (gen_vec_cmp (mask, operands[3], operands[4], operands[5])); - emit_insn (gen_vcond_mask_ (operands[0], operands[1], - operands[2], mask)); + emit_insn (gen_vcond_mask_ (operands[0], operands[1], + operands[2], mask)); DONE; }) @@ -2752,7 +2752,7 @@ (define_expand "vcondumode); + rtx mask = gen_reg_rtx (mode); enum rtx_code code = GET_CODE (operands[3]); /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert @@ -2767,8 +2767,8 @@ (define_expand "vcondu ( mask, operands[3], operands[4], operands[5])); - emit_insn (gen_vcond_mask_ (operands[0], operands[1], - operands[2], mask)); + emit_insn (gen_vcond_mask_ (operands[0], operands[1], + operands[2], mask)); DONE; }) @@ -4208,9 +4208,9 @@ (define_insn "aarch64_qshrn_n ;; have different ideas of what should be passed to this pattern. (define_insn "aarch64_cm" - [(set (match_operand: 0 "register_operand" "=w,w") - (neg: - (COMPARISONS: + [(set (match_operand: 0 "register_operand" "=w,w") + (neg: + (COMPARISONS: (match_operand:VDQ_I 1 "register_operand" "w,w") (match_operand:VDQ_I 2 "aarch64_simd_reg_or_zero" "w,ZDz") )))] @@ -4273,9 +4273,9 @@ (define_insn "*aarch64_cmdi" ;; cm(hs|hi) (define_insn "aarch64_cm" - [(set (match_operand: 0 "register_operand" "=w") - (neg: - (UCOMPARISONS: + [(set (match_operand: 0 "register_operand" "=w") + (neg: + (UCOMPARISONS: (match_operand:VDQ_I 1 "register_operand" "w") (match_operand:VDQ_I 2 "register_operand" "w") )))] @@ -4340,14 +4340,14 @@ (define_insn "*aarch64_cmdi" ;; plus (eq (and x y) 0) -1. (define_insn "aarch64_cmtst" - [(set (match_operand: 0 "register_operand" "=w") - (plus: - (eq: + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (eq: (and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w") (match_operand:VDQ_I 2 "register_operand" "w")) (match_operand:VDQ_I 3 "aarch64_simd_imm_zero")) - (match_operand: 4 "aarch64_simd_imm_minus_one"))) + (match_operand: 4 "aarch64_simd_imm_minus_one"))) ] "TARGET_SIMD" "cmtst\t%0, %1, %2" @@ -4408,9 +4408,9 @@ (define_insn "*aarch64_cmtstdi" ;; fcm(eq|ge|gt|le|lt) (define_insn "aarch64_cm" - [(set (match_operand: 0 "register_operand" "=w,w") - (neg: - (COMPARISONS: + [(set (match_operand: 0 "register_operand" "=w,w") + (neg: + (COMPARISONS: (match_operand:VHSDF_HSDF 1 "register_operand" "w,w") (match_operand:VHSDF_HSDF 2 "aarch64_simd_reg_or_zero" "w,YDz") )))] @@ -4426,9 +4426,9 @@ (define_insn "aarch64_cm" ;; generating fac(ge|gt). (define_insn "aarch64_fac" - [(set (match_operand: 0 "register_operand" "=w") - (neg: - (FAC_COMPARISONS: + [(set (match_operand: 0 "register_operand" "=w") + (neg: + (FAC_COMPARISONS: (abs:VHSDF_HSDF (match_operand:VHSDF_HSDF 1 "register_operand" "w")) (abs:VHSDF_HSDF @@ -5130,7 +5130,7 @@ (define_expand "vec_perm_const" [(match_operand:VALL_F16 0 "register_operand") (match_operand:VALL_F16 1 "register_operand") (match_operand:VALL_F16 2 "register_operand") - (match_operand: 3)] + (match_operand: 3)] "TARGET_SIMD" { if (aarch64_expand_vec_perm_const (operands[0], operands[1],