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[81.169.180.215]) by mx.google.com with ESMTP id a9si6117478eda.237.2017.08.26.02.01.24; Sat, 26 Aug 2017 02:01:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=Vm3fLlM3; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 05C04C22082; Sat, 26 Aug 2017 09:00:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E75C9C2208A; Sat, 26 Aug 2017 08:58:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 89DA2C2206F; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 2167BC22072 for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANO031195; Sat, 26 Aug 2017 17:58:12 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANO031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737892; bh=qDMTszA/zXp1b9Y23ziItA9FQB5oRNryjscBY0I7pcg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vm3fLlM3NF9KyOJEFsEV3VmRD7zvKG7h84KW5qHjPDeXvBPOS9WkQJAupTVI0OLDB 4eogUxzU/FLRrPPCEADvF/I1v8/32D5tupd9NmqHYwYpcaZkJut2AnCISZyZXGRcFh +BvzjqJGKgbXCx6zbwvuRu9kXNIzugNvZ5dmvaqLgivb6RrODSUKp72xB0nfIE/kfe Qig0+FfRqTt5rc3//WR7RDtQhHAwGBpHQJmYMOfOd3pxMrIiWo15iDVfNW7CzDArKS ONNyguAoWM5zNUMJ4X2hnnElwDg4PFmyQwQe393MXn2LRpviM4trBpz5AXOvUncqWt AGs0iO0FLO0KA== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:58:00 +0900 Message-Id: <1503737883-14236-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 3/6] ARM: uniphier: add PLL settings for PXs3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-pxs3.c | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c index 201d3517a86a..e84d52b80f3b 100644 --- a/arch/arm/mach-uniphier/clk/pll-pxs3.c +++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c @@ -1,9 +1,64 @@ /* + * Copyright (C) 2017 Socionext Inc. + * * SPDX-License-Identifier: GPL-2.0+ */ +#include + #include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ +#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) +#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) +#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) +#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) void uniphier_pxs3_pll_init(void) { + uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + /* do nothing for SPLL */ + uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + mdelay(1); + + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); + + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); + + uniphier_ld20_dspll_init(SC_VPLL8KCTRL); }