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[209.132.180.131]) by mx.google.com with ESMTPS id v69si9100797pfk.576.2017.08.28.01.29.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 01:29:02 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-460998-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=mc/NmP2D; spf=pass (google.com: domain of gcc-patches-return-460998-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-460998-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=S2th7Qb+NKruXH9TnwifFb7pyiEvJcJJH1+ghpNU01dvopDkIP8Nn 1beDNR+BuC9O021a5AKwZhqn3auwSQMsKyl9hEhUYnrS6LHWVX7uNmGUEca7Hpaw Vsvs/RF+pvu2xR6YU43jqL71fA6ho6GzcA4cp4pI3bgCnCTzxbJIAY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=ufkluHz+mkg7F6JtDJR95VUFobc=; b=mc/NmP2DNA6Xh4dLdi4l /FlNAa1BxLAa6cB/G0b7eEaXCSoaSBtQz3dPobSuA/8Tfg025wZ3P+Fo0dY4/0HT oKZ6n6jyezoNHl4AjeSCYn1sqwLFzerWSgPQUDtBbRGmM6Rz2zLD164v5pSmmAjr UGsiNhfz/yq3VxG/VAQbf4s= Received: (qmail 8551 invoked by alias); 28 Aug 2017 08:28:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 103822 invoked by uid 89); 28 Aug 2017 08:26:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f47.google.com Received: from mail-wm0-f47.google.com (HELO mail-wm0-f47.google.com) (74.125.82.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 28 Aug 2017 08:26:23 +0000 Received: by mail-wm0-f47.google.com with SMTP id y71so24692108wmd.0 for ; Mon, 28 Aug 2017 01:26:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:date:message-id :user-agent:mime-version; bh=oxgA68k1PPSSZ/hFuw/n37IPUHq3S8EPqmqqa3iTZA4=; b=BxQIhHadM01BzprXz5l/5zY+il9EkTXt7SU2Iq3qcaTokxK8i/4kuUtA7rDWIwqAmG 5J1CC9Jd7Dkxs5Trc8PuN41aZKekJ+2VfUtdGf4Hp3ywbdE6dXnpURgiIp82NET5WSdR M6wrTMFXrQq60lOiKirwsBq6jKz3M6+MBNJ+ZrUW3RADkS2KJ+Pk2Wiazi/YzxpsriTq bLqnNa8PNMu3cWiFtXYS1wpN5z8KW7dlx6i4iVyW7nBRCYJywehw4FywmGMGeobDXeX1 MOOjkOiUhOQlJhA/0zPrvQJ4WdJFMAjJSCAwcfKKyLkc08AbaRF3YwitdpqSotU7IeXO tHMA== X-Gm-Message-State: AHYfb5gZOGAaCRJSfM8nLX7DY4/wpp9ZolA4JzNl/rO5QKFr9INGRygz su2MbBTn+hfuxT+YDoPKsQ== X-Received: by 10.28.150.215 with SMTP id y206mr3004887wmd.164.1503908780158; Mon, 28 Aug 2017 01:26:20 -0700 (PDT) Received: from localhost ([95.145.139.63]) by smtp.gmail.com with ESMTPSA id p4sm9321085wrd.50.2017.08.28.01.26.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Aug 2017 01:26:19 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: Add wider_subreg_mode helper functions Date: Mon, 28 Aug 2017 09:26:26 +0100 Message-ID: <87o9r0t7wt.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 This patch adds helper functions that say which of the two modes involved in a subreg is the larger, preferring the outer mode in the event of a tie. It also converts IRA and reload to track modes instead of byte sizes, since this is slightly more convenient when variable-sized modes are added later. Tested on aarch64-linux-gnu and x86_64-linux-gnu, and by checking there was no change in the testsuite assembly output for at least one target per CPU. OK to install? Richard 2017-08-28 Richard Sandiford Alan Hayward David Sherwood gcc/ * rtl.h (wider_subreg_mode): New function. * ira.h (ira_sort_regnos_for_alter_reg): Take a machine_mode * rather than an unsigned int *. * ira-color.c (regno_max_ref_width): Replace with... (regno_max_ref_mode): ...this new variable. (coalesced_pseudo_reg_slot_compare): Update accordingly. Use wider_subreg_mode. (ira_sort_regnos_for_alter_reg): Likewise. Take a machine_mode * rather than an unsigned int *. * lra-constraints.c (uses_hard_regs_p): Use wider_subreg_mode. (process_alt_operands): Likewise. (invariant_p): Likewise. * lra-spills.c (assign_mem_slot): Likewise. (add_pseudo_to_slot): Likewise. * lra.c (collect_non_operand_hard_regs): Likewise. (add_regs_to_insn_regno_info): Likewise. * reload1.c (regno_max_ref_width): Replace with... (regno_max_ref_mode): ...this new variable. (reload): Update accordingly. Update call to ira_sort_regnos_for_alter_reg. (alter_reg): Update to use regno_max_ref_mode. Call wider_subreg_mode. (init_eliminable_invariants): Update to use regno_max_ref_mode. (scan_paradoxical_subregs): Likewise. Index: gcc/rtl.h =================================================================== --- gcc/rtl.h 2017-08-28 09:23:51.181220876 +0100 +++ gcc/rtl.h 2017-08-28 09:23:56.230220860 +0100 @@ -2840,6 +2840,24 @@ subreg_lowpart_offset (machine_mode oute GET_MODE_SIZE (innermode)); } +/* Given that a subreg has outer mode OUTERMODE and inner mode INNERMODE, + return the mode that is big enough to hold both the outer and inner + values. Prefer the outer mode in the event of a tie. */ + +inline machine_mode +wider_subreg_mode (machine_mode outermode, machine_mode innermode) +{ + return partial_subreg_p (outermode, innermode) ? innermode : outermode; +} + +/* Likewise for subreg X. */ + +inline machine_mode +wider_subreg_mode (const_rtx x) +{ + return wider_subreg_mode (GET_MODE (x), GET_MODE (SUBREG_REG (x))); +} + extern unsigned int subreg_size_highpart_offset (unsigned int, unsigned int); /* Return the SUBREG_BYTE for an OUTERMODE highpart of an INNERMODE value. */ Index: gcc/ira.h =================================================================== --- gcc/ira.h 2017-08-28 09:22:51.676686496 +0100 +++ gcc/ira.h 2017-08-28 09:23:56.227520860 +0100 @@ -195,7 +195,7 @@ extern void ira_set_pseudo_classes (bool extern void ira_expand_reg_equiv (void); extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *); -extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *); +extern void ira_sort_regnos_for_alter_reg (int *, int, machine_mode *); extern void ira_mark_allocation_change (int); extern void ira_mark_memory_move_deletion (int, int); extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *, Index: gcc/ira-color.c =================================================================== --- gcc/ira-color.c 2017-08-28 09:22:51.676686496 +0100 +++ gcc/ira-color.c 2017-08-28 09:23:56.226620860 +0100 @@ -3908,7 +3908,7 @@ coalesced_pseudo_reg_freq_compare (const /* Widest width in which each pseudo reg is referred to (via subreg). It is used for sorting pseudo registers. */ -static unsigned int *regno_max_ref_width; +static machine_mode *regno_max_ref_mode; /* Sort pseudos according their slot numbers (putting ones with smaller numbers first, or last when the frame pointer is not @@ -3921,7 +3921,7 @@ coalesced_pseudo_reg_slot_compare (const ira_allocno_t a1 = ira_regno_allocno_map[regno1]; ira_allocno_t a2 = ira_regno_allocno_map[regno2]; int diff, slot_num1, slot_num2; - int total_size1, total_size2; + machine_mode mode1, mode2; if (a1 == NULL || ALLOCNO_HARD_REGNO (a1) >= 0) { @@ -3936,11 +3936,11 @@ coalesced_pseudo_reg_slot_compare (const if ((diff = slot_num1 - slot_num2) != 0) return (frame_pointer_needed || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff); - total_size1 = MAX (PSEUDO_REGNO_BYTES (regno1), - regno_max_ref_width[regno1]); - total_size2 = MAX (PSEUDO_REGNO_BYTES (regno2), - regno_max_ref_width[regno2]); - if ((diff = total_size2 - total_size1) != 0) + mode1 = wider_subreg_mode (PSEUDO_REGNO_MODE (regno1), + regno_max_ref_mode[regno1]); + mode2 = wider_subreg_mode (PSEUDO_REGNO_MODE (regno2), + regno_max_ref_mode[regno2]); + if ((diff = GET_MODE_SIZE (mode2) - GET_MODE_SIZE (mode1)) != 0) return diff; return regno1 - regno2; } @@ -4144,7 +4144,7 @@ coalesce_spill_slots (ira_allocno_t *spi reload. */ void ira_sort_regnos_for_alter_reg (int *pseudo_regnos, int n, - unsigned int *reg_max_ref_width) + machine_mode *reg_max_ref_mode) { int max_regno = max_reg_num (); int i, regno, num, slot_num; @@ -4225,10 +4225,14 @@ ira_sort_regnos_for_alter_reg (int *pseu ira_assert (ALLOCNO_HARD_REGNO (a) < 0); ALLOCNO_HARD_REGNO (a) = -slot_num; if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) - fprintf (ira_dump_file, " a%dr%d(%d,%d)", - ALLOCNO_NUM (a), ALLOCNO_REGNO (a), ALLOCNO_FREQ (a), - MAX (PSEUDO_REGNO_BYTES (ALLOCNO_REGNO (a)), - reg_max_ref_width[ALLOCNO_REGNO (a)])); + { + machine_mode mode = wider_subreg_mode + (PSEUDO_REGNO_MODE (ALLOCNO_REGNO (a)), + reg_max_ref_mode[ALLOCNO_REGNO (a)]); + fprintf (ira_dump_file, " a%dr%d(%d,%d)", + ALLOCNO_NUM (a), ALLOCNO_REGNO (a), ALLOCNO_FREQ (a), + GET_MODE_SIZE (mode)); + } if (a == allocno) break; @@ -4239,7 +4243,7 @@ ira_sort_regnos_for_alter_reg (int *pseu ira_spilled_reg_stack_slots_num = slot_num - 1; ira_free (spilled_coalesced_allocnos); /* Sort regnos according the slot numbers. */ - regno_max_ref_width = reg_max_ref_width; + regno_max_ref_mode = reg_max_ref_mode; qsort (pseudo_regnos, n, sizeof (int), coalesced_pseudo_reg_slot_compare); FOR_EACH_ALLOCNO (a, ai) ALLOCNO_ADD_DATA (a) = NULL; Index: gcc/lra-constraints.c =================================================================== --- gcc/lra-constraints.c 2017-08-28 09:23:40.551863444 +0100 +++ gcc/lra-constraints.c 2017-08-28 09:23:56.227520860 +0100 @@ -1772,10 +1772,9 @@ uses_hard_regs_p (rtx x, HARD_REG_SET se mode = GET_MODE (x); if (code == SUBREG) { + mode = wider_subreg_mode (x); x = SUBREG_REG (x); code = GET_CODE (x); - if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) - mode = GET_MODE (x); } if (REG_P (x)) @@ -1953,10 +1952,8 @@ process_alt_operands (int only_alternati biggest_mode[nop] = GET_MODE (op); if (GET_CODE (op) == SUBREG) { + biggest_mode[nop] = wider_subreg_mode (op); operand_reg[nop] = reg = SUBREG_REG (op); - if (GET_MODE_SIZE (biggest_mode[nop]) - < GET_MODE_SIZE (GET_MODE (reg))) - biggest_mode[nop] = GET_MODE (reg); } if (! REG_P (reg)) operand_reg[nop] = NULL_RTX; @@ -5665,8 +5662,7 @@ invariant_p (const_rtx x) { x = SUBREG_REG (x); code = GET_CODE (x); - if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) - mode = GET_MODE (x); + mode = wider_subreg_mode (mode, GET_MODE (x)); } if (MEM_P (x)) Index: gcc/lra-spills.c =================================================================== --- gcc/lra-spills.c 2017-08-28 09:23:42.709863597 +0100 +++ gcc/lra-spills.c 2017-08-28 09:23:56.227520860 +0100 @@ -134,8 +134,7 @@ assign_mem_slot (int i) machine_mode mode = GET_MODE (regno_reg_rtx[i]); HOST_WIDE_INT inherent_size = PSEUDO_REGNO_BYTES (i); machine_mode wider_mode - = (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (lra_reg_info[i].biggest_mode) - ? mode : lra_reg_info[i].biggest_mode); + = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); HOST_WIDE_INT total_size = GET_MODE_SIZE (wider_mode); HOST_WIDE_INT adjust = 0; @@ -311,10 +310,8 @@ add_pseudo_to_slot (int regno, int slot_ and a total size which provides room for paradoxical subregs. We need to make sure the size and alignment of the slot are sufficient for both. */ - machine_mode mode = (GET_MODE_SIZE (PSEUDO_REGNO_MODE (regno)) - >= GET_MODE_SIZE (lra_reg_info[regno].biggest_mode) - ? PSEUDO_REGNO_MODE (regno) - : lra_reg_info[regno].biggest_mode); + machine_mode mode = wider_subreg_mode (PSEUDO_REGNO_MODE (regno), + lra_reg_info[regno].biggest_mode); unsigned int align = spill_slot_alignment (mode); slots[slot_num].align = MAX (slots[slot_num].align, align); slots[slot_num].size = MAX (slots[slot_num].size, GET_MODE_SIZE (mode)); Index: gcc/lra.c =================================================================== --- gcc/lra.c 2017-08-28 09:23:38.966863332 +0100 +++ gcc/lra.c 2017-08-28 09:23:56.229320860 +0100 @@ -831,12 +831,11 @@ collect_non_operand_hard_regs (rtx *x, l subreg_p = false; if (code == SUBREG) { + mode = wider_subreg_mode (op); if (read_modify_subreg_p (op)) subreg_p = true; op = SUBREG_REG (op); code = GET_CODE (op); - if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (op))) - mode = GET_MODE (op); } if (REG_P (op)) { @@ -1426,12 +1425,11 @@ add_regs_to_insn_regno_info (lra_insn_re subreg_p = false; if (GET_CODE (x) == SUBREG) { + mode = wider_subreg_mode (x); if (read_modify_subreg_p (x)) subreg_p = true; x = SUBREG_REG (x); code = GET_CODE (x); - if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) - mode = GET_MODE (x); } if (REG_P (x)) { Index: gcc/reload1.c =================================================================== --- gcc/reload1.c 2017-08-28 09:23:42.710863597 +0100 +++ gcc/reload1.c 2017-08-28 09:23:56.229320860 +0100 @@ -97,8 +97,8 @@ #define spill_indirect_levels \ in the current insn. */ static HARD_REG_SET reg_is_output_reload; -/* Widest width in which each pseudo reg is referred to (via subreg). */ -static unsigned int *reg_max_ref_width; +/* Widest mode in which each pseudo reg is referred to (via subreg). */ +static machine_mode *reg_max_ref_mode; /* Vector to remember old contents of reg_renumber before spilling. */ static short *reg_old_renumber; @@ -832,7 +832,7 @@ reload (rtx_insn *first, int global) if (ira_conflicts_p) /* Ask IRA to order pseudo-registers for better stack slot sharing. */ - ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width); + ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode); for (i = 0; i < n; i++) alter_reg (temp_pseudo_reg_arr[i], -1, false); @@ -1254,7 +1254,7 @@ reload (rtx_insn *first, int global) /* Indicate that we no longer have known memory locations or constants. */ free_reg_equiv (); - free (reg_max_ref_width); + free (reg_max_ref_mode); free (reg_old_renumber); free (pseudo_previous_regs); free (pseudo_forbidden_regs); @@ -2146,8 +2146,9 @@ alter_reg (int i, int from_reg, bool don machine_mode mode = GET_MODE (regno_reg_rtx[i]); unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); unsigned int inherent_align = GET_MODE_ALIGNMENT (mode); - unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); - unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT; + machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]); + unsigned int total_size = GET_MODE_SIZE (wider_mode); + unsigned int min_align = GET_MODE_BITSIZE (reg_max_ref_mode[i]); int adjust = 0; something_was_spilled = true; @@ -4085,9 +4086,9 @@ init_eliminable_invariants (rtx_insn *fi grow_reg_equivs (); if (do_subregs) - reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); + reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno); else - reg_max_ref_width = NULL; + reg_max_ref_mode = NULL; num_eliminable_invariants = 0; @@ -4406,7 +4407,7 @@ finish_spills (int global) return something_changed; } -/* Find all paradoxical subregs within X and update reg_max_ref_width. */ +/* Find all paradoxical subregs within X and update reg_max_ref_mode. */ static void scan_paradoxical_subregs (rtx x) @@ -4429,13 +4430,14 @@ scan_paradoxical_subregs (rtx x) return; case SUBREG: - if (REG_P (SUBREG_REG (x)) - && (GET_MODE_SIZE (GET_MODE (x)) - > reg_max_ref_width[REGNO (SUBREG_REG (x))])) + if (REG_P (SUBREG_REG (x))) { - reg_max_ref_width[REGNO (SUBREG_REG (x))] - = GET_MODE_SIZE (GET_MODE (x)); - mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x)); + unsigned int regno = REGNO (SUBREG_REG (x)); + if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x))) + { + reg_max_ref_mode[regno] = GET_MODE (x); + mark_home_live_1 (regno, GET_MODE (x)); + } } return;