From patchwork Fri Aug 31 06:33:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 11123 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5C5EC23E56 for ; Fri, 31 Aug 2012 06:36:32 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7C08EA193A7 for ; Fri, 31 Aug 2012 06:35:54 +0000 (UTC) Received: by iafj25 with SMTP id j25so4288419iaf.11 for ; Thu, 30 Aug 2012 23:36:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=3td0JPJxnT2Me4GwGdTt7atjhFmosV1V786sbC1zeiM=; b=nj922FZNJT+uKtXax/oZvD7+vq9Zd923HBQAKlCAyXAdKjM0Wl+GXU6b9DQyU3QbSF 6J/fqTH/3NLInGVAwUDn6olo92TKXq+kvTPhU6b3s85E3m5r1E9Vh+te+XlN5oudj95R 1ZosAQBVB8Qoz3+tpXjQu0TWTxjzjj3H7zKeLNUEI90eayRDZvR6TDktIvtjj0RMbyf+ HTbBm5yGqylXaofl6aXfd9tVXf0gmLrG7oAUbTWkyR3xr6RJbtAbJW50rAJoaxzD0OjK s4lvpnqfrB8to05Cyi19QVHdTZUV6M9M3LmjtfLQbMgUnf1ZWeM27Mj8hKOwTsBU3Iqo ePGQ== Received: by 10.50.7.212 with SMTP id l20mr1166557iga.43.1346394991307; Thu, 30 Aug 2012 23:36:31 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp50198igc; Thu, 30 Aug 2012 23:36:30 -0700 (PDT) Received: by 10.68.203.67 with SMTP id ko3mr15804303pbc.126.1346394990674; Thu, 30 Aug 2012 23:36:30 -0700 (PDT) Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id iw4si6868494pbc.231.2012.08.30.23.36.30 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 30 Aug 2012 23:36:30 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of tushar.behera@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of tushar.behera@linaro.org) smtp.mail=tushar.behera@linaro.org Received: by pbcmd12 with SMTP id md12so4716860pbc.37 for ; Thu, 30 Aug 2012 23:36:30 -0700 (PDT) Received: by 10.68.138.163 with SMTP id qr3mr11200448pbb.161.1346394990236; Thu, 30 Aug 2012 23:36:30 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id qp6sm2841954pbc.55.2012.08.30.23.36.27 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 30 Aug 2012 23:36:29 -0700 (PDT) From: Tushar Behera To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, chander.kashyap@linaro.org, patches@linaro.org, Annamalai Lakshmanan Subject: [PATCH] Origen: Add default clock settings for multimedia IPs Date: Fri, 31 Aug 2012 12:03:58 +0530 Message-Id: <1346394838-17627-1-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQl/thnhDKbrq7g0cwQSSTJbamejuTubJoBbOM18S9Lw4nxOWn0PYwxaeewLBuBrddLunmIy From: Annamalai Lakshmanan Added clock settings for MFC, FIMC, FB and G3D. They are clocked to maximum respective frequencies as per datasheet. Signed-off-by: Annamalai Lakshmanan Signed-off-by: Giridhar Maruthy Signed-off-by: Inderpal Singh Signed-off-by: Tushar Behera --- board/samsung/origen/lowlevel_init.S | 37 ++++++++++++++++- board/samsung/origen/origen_setup.h | 74 ++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 1 deletions(-) diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S index 9283201..9daa0da 100644 --- a/board/samsung/origen/lowlevel_init.S +++ b/board/samsung/origen/lowlevel_init.S @@ -158,7 +158,22 @@ system_clock_init: ldr r2, =CLK_SRC_PERIL0_OFFSET str r1, [r0, r2] - /* FIMD0 */ + /* CAM , FIMC 0-3 */ + ldr r1, =CLK_SRC_CAM_VAL + ldr r2, =CLK_SRC_CAM_OFFSET + str r1, [r0, r2] + + /* MFC */ + ldr r1, =CLK_SRC_MFC_VAL + ldr r2, =CLK_SRC_MFC_OFFSET + str r1, [r0, r2] + + /* G3D */ + ldr r1, =CLK_SRC_G3D_VAL + ldr r2, =CLK_SRC_G3D_OFFSET + str r1, [r0, r2] + + /* LCD0 */ ldr r1, =CLK_SRC_LCD0_VAL ldr r2, =CLK_SRC_LCD0_OFFSET str r1, [r0, r2] @@ -223,6 +238,26 @@ system_clock_init: ldr r2, =CLK_DIV_PERIL0_OFFSET str r1, [r0, r2] + /* CAM, FIMC 0-3: CAM Clock Divisors */ + ldr r1, =CLK_DIV_CAM_VAL + ldr r2, =CLK_DIV_CAM_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_MFC: MFC Clock Divisors */ + ldr r1, =CLK_DIV_MFC_VAL + ldr r2, =CLK_DIV_MFC_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_G3D: G3D Clock Divisors */ + ldr r1, =CLK_DIV_G3D_VAL + ldr r2, =CLK_DIV_G3D_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_LCD0: LCD0 Clock Divisors */ + ldr r1, =CLK_DIV_LCD0_VAL + ldr r2, =CLK_DIV_LCD0_OFFSET + str r1, [r0, r2] + /* Set PLL locktime */ ldr r1, =PLL_LOCKTIME ldr r2, =APLL_LOCK_OFFSET diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h index 94cccca..930b948 100644 --- a/board/samsung/origen/origen_setup.h +++ b/board/samsung/origen/origen_setup.h @@ -53,7 +53,18 @@ #define CLK_DIV_FSYS2_OFFSET 0xC548 #define CLK_DIV_FSYS3_OFFSET 0xC54C +#define CLK_SRC_CAM_OFFSET 0xC220 +#define CLK_SRC_TV_OFFSET 0xC224 +#define CLK_SRC_MFC_OFFSET 0xC228 +#define CLK_SRC_G3D_OFFSET 0xC22C +#define CLK_SRC_LCD0_OFFSET 0xC234 #define CLK_SRC_PERIL0_OFFSET 0xC250 + +#define CLK_DIV_CAM_OFFSET 0xC520 +#define CLK_DIV_TV_OFFSET 0xC524 +#define CLK_DIV_MFC_OFFSET 0xC528 +#define CLK_DIV_G3D_OFFSET 0xC52C +#define CLK_DIV_LCD0_OFFSET 0xC534 #define CLK_DIV_PERIL0_OFFSET 0xC550 #define CLK_SRC_LCD0_OFFSET 0xC234 @@ -353,6 +364,65 @@ | (UART1_RATIO << 4) \ | (UART0_RATIO << 0)) +/* Clock Source CAM/FIMC */ +/* CLK_SRC_CAM */ +#define CAM0_SEL_XUSBXTI 1 +#define CAM1_SEL_XUSBXTI 1 +#define CSIS0_SEL_XUSBXTI 1 +#define CSIS1_SEL_XUSBXTI 1 + +#define FIMC_SEL_SCLKMPLL 6 +#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL +#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL +#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL +#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL + +#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \ + | (CSIS0_SEL_XUSBXTI << 24) \ + | (CAM1_SEL_XUSBXTI << 20) \ + | (CAM0_SEL_XUSBXTI << 16) \ + | (FIMC3_LCLK_SEL << 12) \ + | (FIMC2_LCLK_SEL << 8) \ + | (FIMC1_LCLK_SEL << 4) \ + | (FIMC0_LCLK_SEL << 0)) + +/* SCLK CAM */ +/* CLK_DIV_CAM */ +#define FIMC0_LCLK_RATIO 4 +#define FIMC1_LCLK_RATIO 4 +#define FIMC2_LCLK_RATIO 4 +#define FIMC3_LCLK_RATIO 4 +#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \ + | (FIMC2_LCLK_RATIO << 8) \ + | (FIMC1_LCLK_RATIO << 4) \ + | (FIMC0_LCLK_RATIO << 0)) + +/* SCLK MFC */ +/* CLK_SRC_MFC */ +#define MFC_SEL_MPLL 0 +#define MOUTMFC_0 0 +#define MFC_SEL MOUTMFC_0 +#define MFC_0_SEL MFC_SEL_MPLL +#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL)) + + +/* CLK_DIV_MFC */ +#define MFC_RATIO 3 +#define CLK_DIV_MFC_VAL (MFC_RATIO) + +/* SCLK G3D */ +/* CLK_SRC_G3D */ +#define G3D_SEL_MPLL 0 +#define MOUTG3D_0 0 +#define G3D_SEL MOUTG3D_0 +#define G3D_0_SEL G3D_SEL_MPLL +#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL)) + +/* CLK_DIV_G3D */ +#define G3D_RATIO 1 +#define CLK_DIV_G3D_VAL (G3D_RATIO) + +/* SCLK LCD0 */ /* CLK_SRC_LCD0 */ #define FIMD_SEL_SCLKMPLL 6 #define MDNIE0_SEL_XUSBXTI 1 @@ -363,6 +433,10 @@ | (MDNIE0_SEL_XUSBXTI << 4) \ | (FIMD_SEL_SCLKMPLL << 0)) +/* CLK_DIV_LCD0 */ +#define FIMD0_RATIO 4 +#define CLK_DIV_LCD0_VAL (FIMD0_RATIO) + /* Required period to generate a stable clock output */ /* PLL_LOCK_TIME */ #define PLL_LOCKTIME 0x1C20