[AArch64,obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>

Message ID 1504195434-26009-1-git-send-email-james.greenhalgh@arm.com
State New
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Series
  • [AArch64,obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>
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Commit Message

James Greenhalgh Aug. 31, 2017, 4:03 p.m.
Hi,

The MLA by-element instructions have the same restriction as other by-element
instructions whereby the forms operating on vectors of 16-bit integer data
may only use registers v0-v15. We have an iterator for that, applied to the
other patterns generating this instruction, so use that.

Bootstrap and test OK, Applied as r251568.

Thanks,
James

---
2017-08-31  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix
	register constraint for by-element operand.
	(aarch64_mls_elt_merge<mode>): Likewise.

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index bf2db02..051d2a9 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1072,7 +1072,7 @@ 
   [(set (match_operand:VDQHS 0 "register_operand" "=w")
 	(plus:VDQHS
 	  (mult:VDQHS (vec_duplicate:VDQHS
-		  (match_operand:<VEL> 1 "register_operand" "w"))
+		  (match_operand:<VEL> 1 "register_operand" "<h_con>"))
 		(match_operand:VDQHS 2 "register_operand" "w"))
 	  (match_operand:VDQHS 3 "register_operand" "0")))]
  "TARGET_SIMD"
@@ -1132,7 +1132,7 @@ 
 	(minus:VDQHS
 	  (match_operand:VDQHS 1 "register_operand" "0")
 	  (mult:VDQHS (vec_duplicate:VDQHS
-		  (match_operand:<VEL> 2 "register_operand" "w"))
+		  (match_operand:<VEL> 2 "register_operand" "<h_con>"))
 		(match_operand:VDQHS 3 "register_operand" "w"))))]
   "TARGET_SIMD"
   "mls\t%0.<Vtype>, %3.<Vtype>, %2.<Vetype>[0]"