From patchwork Thu Sep 7 13:28:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 111924 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp100900qge; Thu, 7 Sep 2017 06:34:20 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBJCJJT4VEmEJDRMC9eV06iz3YJbDegte3k0b6069iEk6J5xSYQ2aWZbPURewTN55w5GAAW X-Received: by 10.233.244.72 with SMTP id z8mr3736689qkl.186.1504791260096; Thu, 07 Sep 2017 06:34:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504791260; cv=none; d=google.com; s=arc-20160816; b=IZLUWJAzZPo3hvpAimcE+YZujFIMPm0l08nPXt3o0DI/qT4JIdO6mk/mFBLs8jAYXA zls1JYe2tVZFhgY+ciQZxUBtl5xekBa6GPFvPMIO+jqFnWkn5D6qgIzlo418tuP+mTAF 7iCWXL2f+6sY24vjAjoXU8i0DLgrweB1WBCzP467Gq12hBTQ2fIjCXIlRa94qP4N4NXh FJ4w5rydJBDgDMmEK8A1fIptCw5ZgAxBy6Et3xM5LRQcKSOvGuQQ6N+eqbzNTJFV5GpE FMOvrzgXsYstyq9QaTrlPByo7VcjfDS5PHgRF/iErSu7WrDxevarC0oKExGtZh8nBdHi faCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=OtFNbXChUQo10Gt+A7vqlwuZhbqH+hacYYQmRyxDgDM=; b=ZvTHafAfq4JT1Ihl93mIb5n/h63qUk8fXT24yV1rZvNHc7TcnUoh542E+Y47W3byLG Jik/LCFjFf99mvq0H5+1kd81qe6JSrF5AnngvfEHGpIK+bghOTeraSQG98q84XL0J+mf B6ZZvE2/nIOsKkVrAx9DOCEmws6lBAYBIPBI90DdAGayb3ycFG4S3mPD0+j0+HQ8JXwp pgAY0p3BrqtbMIwLt8pCo3YTbX4qLpxjQHIr7KP5t2J4Vs3tOpeCFt9nQqtK+sE9aGEu csP83J0VW+yjGRYNIsybesCMjTJvpaqXN+NSNwS3h+y1DjzfNRSqC+8zE984XvQJpzNf YLLg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c20si2969422qta.516.2017.09.07.06.34.19 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 07 Sep 2017 06:34:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwwj-0005qF-WF for patch@linaro.org; Thu, 07 Sep 2017 09:34:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56414) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwr2-0000zp-6N for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpwqv-0007cJ-QF for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37186) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpwqv-0007Xf-H6 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:17 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpwqo-0001ZH-Hv for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:28:10 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 14:28:03 +0100 Message-Id: <1504790904-17018-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> References: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/31] target/arm: Add state field, feature bit and migration for v8M secure state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1503414539-28762-4-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 3 +++ target/arm/cpu.c | 4 ++++ target/arm/machine.c | 20 ++++++++++++++++++++ target/arm/translate.c | 8 +++++++- 4 files changed, 34 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9fd5de7..02919a3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -66,6 +66,7 @@ #define ARMV7M_EXCP_MEM 4 #define ARMV7M_EXCP_BUS 5 #define ARMV7M_EXCP_USAGE 6 +#define ARMV7M_EXCP_SECURE 7 #define ARMV7M_EXCP_SVC 11 #define ARMV7M_EXCP_DEBUG 12 #define ARMV7M_EXCP_PENDSV 14 @@ -420,6 +421,7 @@ typedef struct CPUARMState { int exception; uint32_t primask; uint32_t faultmask; + uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; /* Information associated with an exception about to be taken: @@ -1263,6 +1265,7 @@ enum arm_features { ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8b610de..f32317e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -185,6 +185,10 @@ static void arm_cpu_reset(CPUState *s) uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->v7m.secure = true; + } + /* The reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making * it dependent on CPU model. diff --git a/target/arm/machine.c b/target/arm/machine.c index 7b6f9de..f70fcf3 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -235,6 +235,25 @@ static const VMStateDescription vmstate_pmsav8 = { } }; +static bool m_security_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_M_SECURITY); +} + +static const VMStateDescription vmstate_m_security = { + .name = "cpu/m-security", + .version_id = 1, + .minimum_version_id = 1, + .needed = m_security_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -485,6 +504,7 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_pmsav7_rnr, &vmstate_pmsav7, &vmstate_pmsav8, + &vmstate_m_security, NULL } }; diff --git a/target/arm/translate.c b/target/arm/translate.c index e52a6d7..dea0a6f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12232,6 +12232,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, if (arm_feature(env, ARM_FEATURE_M)) { uint32_t xpsr = xpsr_read(env); const char *mode; + const char *ns_status = ""; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + ns_status = env->v7m.secure ? "S " : "NS "; + } if (xpsr & XPSR_EXCP) { mode = "handler"; @@ -12243,13 +12248,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } } - cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s\n", + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", xpsr, xpsr & XPSR_N ? 'N' : '-', xpsr & XPSR_Z ? 'Z' : '-', xpsr & XPSR_C ? 'C' : '-', xpsr & XPSR_V ? 'V' : '-', xpsr & XPSR_T ? 'T' : 'A', + ns_status, mode); } else { uint32_t psr = cpsr_read(env);