From patchwork Thu Sep 7 13:28:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 111928 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp102583qge; Thu, 7 Sep 2017 06:35:37 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAxhjTVpn4a0m1ifGO4JeTaJGt20XCpGpOMLqhlWVMlwrAyptMpovCe6W0IOPMxJuBhlNAk X-Received: by 10.55.52.135 with SMTP id b129mr3843293qka.308.1504791337173; Thu, 07 Sep 2017 06:35:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504791337; cv=none; d=google.com; s=arc-20160816; b=tObbkeX7DTHb29NulbgUikryd47UQHlwIbBI0tJIC8a7zDAIW2CkZOgI3Mtlx+Mhk+ eX9fCQV0oIJZSfXaZSoK3+3/+tPG2dy8q4eZlaOUbdQgqzlEm9Ye34dNQry9YcNj/yM+ 2ZEIqKmQtj8MwBbl/spraHEg6wQIUSpcuCDWrMdDDt5DYS4v2xug0awLqWd0S1c2IALC 6vRPBEHgtFoJ0/ZyhMsN3e9mXIMNEnzyss1HBop9xCCOPr3f77TW2+DBhF7q7yZYIn0m P+7EiUNqOFvIUKC7g5jadMKQdLff0oTDnNQN7kdJwgNKD5eUfolK+pxBwgKVIYtzY0pk WwQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=cO3TQQf2/iQ69tJWGxW3YJHRNH99HA3OT7fSNzSBvA4=; b=QUCZdlvdReVTQDHRr85R0CiP0JIfNaVutwj66rfXbe+zbN6uo265Ll+isQ05rp02YZ c/nnETQDsQLTGT9w5KsnXNTfHnDbb6DvK8svC5oMMUdPI2uQ61T2oumLwUMd/H8xuG/o /aSyzTui5iw81+cKbPQ8t/wE+JmdMhjRsVmuT+VIfPe/TSHfkNWCb/ahaBxuP9hGc//Z midheWQBbqFQ6CtdQWnir7ByfT5cstIl5HIGCPLCXwiO3sxQ3aR/0qpNfr1MWLYZzgL6 ouLL3ptpa+FLGP8tau5DQdChfe2ANpqt0qYf5F+nbjTDyW56M0VhhrYyWLwcs6Q60JwI C7IQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g1si2973922qkd.503.2017.09.07.06.35.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 07 Sep 2017 06:35:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40520 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwxz-0006qu-2c for patch@linaro.org; Thu, 07 Sep 2017 09:35:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwr1-0000zk-HW for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpwqv-0007bk-3e for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37188) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpwqu-0007a4-RD for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:17 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpwqt-0001cQ-Qq for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:28:15 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 14:28:11 +0100 Message-Id: <1504790904-17018-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> References: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/31] target/arm: Make VTOR register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make the VTOR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 13 +++++++------ target/arm/helper.c | 2 +- target/arm/machine.c | 3 ++- 4 files changed, 11 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1d9eb36..cf2331d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -420,7 +420,7 @@ typedef struct CPUARMState { struct { uint32_t other_sp; - uint32_t vecbase; + uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2b0b328..3a1f02d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -403,7 +403,7 @@ static void set_irq_level(void *opaque, int n, int level) } } -static uint32_t nvic_readl(NVICState *s, uint32_t offset) +static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu = s->cpu; uint32_t val; @@ -441,7 +441,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) /* ISRPREEMPT not implemented */ return val; case 0xd08: /* Vector Table Offset. */ - return cpu->env.v7m.vecbase; + return cpu->env.v7m.vecbase[attrs.secure]; case 0xd0c: /* Application Interrupt/Reset Control. */ return 0xfa050000 | (s->prigroup << 8); case 0xd10: /* System Control. */ @@ -617,7 +617,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset) } } -static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) +static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, + MemTxAttrs attrs) { ARMCPU *cpu = s->cpu; @@ -638,7 +639,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) } break; case 0xd08: /* Vector Table Offset. */ - cpu->env.v7m.vecbase = value & 0xffffff80; + cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; break; case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) == 0x05fa) { @@ -944,7 +945,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, break; default: if (size == 4) { - val = nvic_readl(s, offset); + val = nvic_readl(s, offset, attrs); } else { qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read of size %d at offset 0x%x\n", @@ -1025,7 +1026,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, return MEMTX_OK; } if (size == 4) { - nvic_writel(s, offset, value); + nvic_writel(s, offset, value, attrs); return MEMTX_OK; } qemu_log_mask(LOG_GUEST_ERROR, diff --git a/target/arm/helper.c b/target/arm/helper.c index aa64596..4685d50 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6067,7 +6067,7 @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult result; - hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; + hwaddr vec = env->v7m.vecbase[env->v7m.secure] + env->v7m.exception * 4; uint32_t addr; addr = address_space_ldl(cs->as, vec, diff --git a/target/arm/machine.c b/target/arm/machine.c index 5e379ed..923f259 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -114,7 +114,7 @@ static const VMStateDescription vmstate_m = { .minimum_version_id = 4, .needed = m_needed, .fields = (VMStateField[]) { - VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), @@ -254,6 +254,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } };