From patchwork Fri Sep 8 18:23:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 112115 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp660228qgf; Fri, 8 Sep 2017 11:23:32 -0700 (PDT) X-Received: by 10.99.3.74 with SMTP id 71mr3893315pgd.401.1504895012324; Fri, 08 Sep 2017 11:23:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504895012; cv=none; d=google.com; s=arc-20160816; b=QTnBxMysW+v54H+xBxDtTge85TMsLF0RUyBHYnKQ/nRA20WQywepKhYMQdDOU7Svim IPP/UrUl2j4MIVGCvDuDbxo4bYd4wn33jQ0TKab1ivEyX0lVEpHcUdU/a2i6RHkbBhPv CeEYeqBbn1nDOUAMuRDS8AxfXEigKhs4dplxj8sVedMNvFIeJ1k+5jnd9HzGqrAOZ0BR 56CtV4HlTuIQnxLNe8vnBanDlPO/Z2Y3Yk6OkbUedAIkIbJayC05vsfjMR8MuXI6Dehx q1OYhIGKUlhhPmSjb5ivek0+iswmYW/A5P82LTnxfgRd7cb78wA27wnQj+x+dDMCyqu9 NXkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=eVW8wvyi1UlbhjSoHuwV2coUljPbAkSlJdRzULcBHms=; b=GCRnjH12zndlKg80gH9DjIorB0859z2QENzn/eW3Zvxw3sj3/BAYrNfwH1w3P2QYxD cbfQ3PIsYLNQKdZmHn8gabaPGXOT0k/ePoThF9e29I0sD1CF0kazRwczbHrfXERui7Vw NoIrOakToMts9lRzBuyihfgtnn9qUvs9k4IRMxWPfBi1vuI73z1avfluVDwjKq96vRmv 4i35LswtqJep22nkoCzJ6hfQEuxL4kBeJkT7OImdwDyskFLojprQmRmNREbDXcV7LQjY Irio94b23yjUXcGH+gwFfQY2a8CoGEW5aTl2E/ulqdIA9SPKk4qfcMES/rhmVcclH+Qm zWgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gBr2Hh+H; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id u8si1978210pfg.41.2017.09.08.11.23.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Sep 2017 11:23:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gBr2Hh+H; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2CD1321E8799C; Fri, 8 Sep 2017 11:20:39 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wr0-x230.google.com (mail-wr0-x230.google.com [IPv6:2a00:1450:400c:c0c::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7F12321959CAD for ; Fri, 8 Sep 2017 11:20:37 -0700 (PDT) Received: by mail-wr0-x230.google.com with SMTP id o42so6006300wrb.3 for ; Fri, 08 Sep 2017 11:23:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+NuIdr5fN/b4VfSbvirBXkWPSBP7VC+NrrPgNCWJZV8=; b=gBr2Hh+HISVn4qFoe+07pBftmYQB+yCwYSS4OwWxAaP3nTv1TkU/juX38E2jHIfr82 XtxTVfcWZDiMvS5sNTaVK6hb2qwtEe0ao/UzsFuYyFAnZc8EdWx5sQ+b3zikvBHyuRLl u3w2wgjA9FyS1wkHBGa0WK+w30UhEKq2Ovyvc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+NuIdr5fN/b4VfSbvirBXkWPSBP7VC+NrrPgNCWJZV8=; b=n6UbzddMp/E9YV3inVh1Q+XWPViApK1yFphMsSpgfe1Vfe9NOaUzAE4rNldP5a0+e7 GYvjQsjDkZV16fxCGJ/C6RSkt1JSIUQAOlNnmngXuhCi1p+OoHpRJKd4DfZwKXdWLpLy SQcXmja/wGsz9mQfe+G196/hl8cn+lhEjnp72nAzTs8m6vS+Xct3FnQJk5JxslBvQTuy wgqi34OsutTIaODa7C9OyWsn2EiveuPif4pABletmLlLkcfYsKG6JMRDLf+veE8K2GV/ qnGFNMDDXyBr3dG6ZKNFrgk0bf61yAYRTzcBm42NYJzWkOXaeKFYXSOxdkVwzbHjJ/8Y d2dQ== X-Gm-Message-State: AHPjjUiQzzBXlbs6DxJKRqhrbf/xvK3ZD7ujjv2N32pgxjumKT2IP3DA 1Y1coj40lKvrUi/siV5pPA== X-Google-Smtp-Source: ADKCNb4Q1oAxztZtJ4cJZpV07M6vg/xboJ6PgjX6nn+Uu4lH6p6c3k28PJlHlEZbtC5v5GdpdiVPfg== X-Received: by 10.223.196.170 with SMTP id m39mr3053241wrf.44.1504895008406; Fri, 08 Sep 2017 11:23:28 -0700 (PDT) Received: from localhost.localdomain ([154.151.223.220]) by smtp.gmail.com with ESMTPSA id s196sm3254354wmb.6.2017.09.08.11.23.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Sep 2017 11:23:27 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 8 Sep 2017 19:23:02 +0100 Message-Id: <20170908182315.9591-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170908182315.9591-1-ard.biesheuvel@linaro.org> References: <20170908182315.9591-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, methavanitpong.pipat@socionext.com, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a package .DEC description for Synquacer with an [Includes] section, and add header files containing descriptions of the platform's memory map and PCIe configuration. No code yet. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h | 65 ++++++++++++++++++++ Silicon/Socionext/Synquacer/Include/Platform/Pcie.h | 63 +++++++++++++++++++ Silicon/Socionext/Synquacer/Synquacer.dec | 22 +++++++ 3 files changed, 150 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h new file mode 100644 index 000000000000..1b5393c32f1d --- /dev/null +++ b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h @@ -0,0 +1,65 @@ +/** @file + PCI memory configuration for Synquacer + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_ +#define _SYNQUACER_PLATFORM_MEMORYMAP_H_ + +// Memory mapped SPI NOR +#define SYNQUACER_SPI_NOR_BASE 0x08000000 +#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB + +// On-Chip non-secure ROM +#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F000000 +#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB + +// On-Chip Peripherals +#define SYNQUACER_PERIPHERALS_BASE 0x20000000 +#define SYNQUACER_PERIPHERALS_SZ 0x0E000000 + +// On-Chip non-secure SRAM +#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E000000 +#define SYNQUACER_NON_SECURE_SRAM_SZ SIZE_32KB + +// GIC-500 +#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB +#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase) +#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB + +// eMMC(SDH30) +#define SYNQUACER_EMMC_BASE 0x52300000 +#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB + +#define SYNQUACER_EEPROM_BASE 0x10000000 +#define SYNQUACER_EEPROM_BASE_SZ SIZE_64KB + +// NETSEC +#define SYNQUACER_NETSEC_BASE 0x522D0000 +#define SYNQUACER_NETSEC_BASE_SZ SIZE_64KB + +#define SYNQUACER_SYSTEM_MEMORY_1_BASE 0x80000000 +#define SYNQUACER_SYSTEM_MEMORY_1_SZ (SIZE_2GB - SIZE_16MB) + +#define SYNQUACER_SYSTEM_MEMORY_2_BASE 0x0880000000ULL +#define SYNQUACER_SYSTEM_MEMORY_2_SZ (SIZE_32GB - SIZE_2GB) + +#define SYNQUACER_SYSTEM_MEMORY_3_BASE 0x8800000000ULL +#define SYNQUACER_SYSTEM_MEMORY_3_SZ SIZE_32GB + +// PCI +#define SYNQUACER_PCIE_BASE 0x58200000 +#define SYNQUACER_PCIE_SIZE 0x00200000 + +#endif diff --git a/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h new file mode 100644 index 000000000000..f7bdc13ad915 --- /dev/null +++ b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h @@ -0,0 +1,63 @@ +/** @file + PCI memory configuration for Synquacer + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_PCI_H_ +#define _SYNQUACER_PLATFORM_PCI_H_ + +#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000 +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000 +#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000 + +#define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 +#define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e + +#define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff +#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE + +#define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 +#define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff +#define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000 + +#define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000 +#define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff +#define SYNQUACER_PCI_SEG0_MMIO64_SIZE 0x100000000 + +#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000 +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000 +#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000 + +#define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 +#define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e + +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff +#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE + +#define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 +#define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff +#define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000 + +#define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000 +#define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff +#define SYNQUACER_PCI_SEG1_MMIO64_SIZE 0x100000000 + +#endif diff --git a/Silicon/Socionext/Synquacer/Synquacer.dec b/Silicon/Socionext/Synquacer/Synquacer.dec new file mode 100644 index 000000000000..955a056a8d59 --- /dev/null +++ b/Silicon/Socionext/Synquacer/Synquacer.dec @@ -0,0 +1,22 @@ +# +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = Synquacer + PACKAGE_GUID = 9c782fd2-7db1-438d-b51c-2155cee2c5cc + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +