[edk2,edk2-platforms,10/14] Silicon/Synquacer: add ACPI support

Message ID 20170908182315.9591-11-ard.biesheuvel@linaro.org
State Superseded
Headers show
Series
  • add support for Socionext Synquacer EVB
Related show

Commit Message

Ard Biesheuvel Sept. 8, 2017, 6:23 p.m.
Enable ACPI support for the SynquacerEvalBoard platform: add descriptions
of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,
including the MSI routing via the GICv3 ITS.

Note that PCIe support is limited to a single bus per RC. Anything beyond
that is unsupported due to a limitation in the hardware that makes it
impossible to expose the PCIe RCs in a fully ECAM compliant manner.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc |  14 +
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf |  13 +
 Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl   | 292 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h          |  58 ++++
 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf        |  58 ++++
 Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl              | 168 +++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc             |  88 ++++++
 Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc             |  98 +++++++
 Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc             | 164 +++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc             | 152 ++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc             |  63 +++++
 Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc             | 127 +++++++++
 12 files changed, 1295 insertions(+)

-- 
2.11.0

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Comments

Leif Lindholm Sept. 11, 2017, 4:33 p.m. | #1
On Fri, Sep 08, 2017 at 07:23:11PM +0100, Ard Biesheuvel wrote:
> Enable ACPI support for the SynquacerEvalBoard platform: add descriptions

> of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,

> including the MSI routing via the GICv3 ITS.

> 

> Note that PCIe support is limited to a single bus per RC. Anything beyond

> that is unsupported due to a limitation in the hardware that makes it

> impossible to expose the PCIe RCs in a fully ECAM compliant manner.

> 


Very few comments here (could we get someone else in to review?).

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> ---

>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc |  14 +

>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf |  13 +

>  Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl   | 292 ++++++++++++++++++++

>  Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h          |  58 ++++

>  Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf        |  58 ++++

>  Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl              | 168 +++++++++++

>  Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc             |  88 ++++++

>  Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc             |  98 +++++++

>  Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc             | 164 +++++++++++

>  Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc             | 152 ++++++++++

>  Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc             |  63 +++++

>  Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc             | 127 +++++++++

>  12 files changed, 1295 insertions(+)

> 

> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc

> index 3d4fbc87e2fa..b2befd2480c4 100644

> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc

> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc

> @@ -475,3 +475,17 @@

>      <LibraryClasses>

>        DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf

>    }

> +

> +  #

> +  # ACPI support

> +  #

> +  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {

> +    <LibraryClasses>

> +      #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf

> +

> +    <PcdsFixedAtBuild>

> +      # support ACPI v5.0 or later

> +      gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20

> +  }

> +  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf

> +  Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf

> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf

> index bd06adf93b3c..35742ad5a347 100644

> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf

> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf

> @@ -183,6 +183,13 @@ READ_LOCK_STATUS   = TRUE

>    INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf

>    INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf

>  

> +  #

> +  # ACPI support

> +  #

> +  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf

> +  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf

> +  INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf

> +

>  [FV.FVMAIN_COMPACT]

>  FvAlignment        = 8

>  ERASE_POLARITY     = 1

> @@ -329,3 +336,9 @@ READ_LOCK_STATUS   = TRUE

>      UI        STRING="$(MODULE_NAME)" Optional

>      VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

>    }

> +

> +[Rule.Common.USER_DEFINED.ACPITABLE]

> +  FILE FREEFORM = $(NAMED_GUID) {

> +    RAW ACPI               |.acpi

> +    RAW ASL                |.aml

> +  }

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl

> new file mode 100644

> index 000000000000..f8d503d65ead

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl

> @@ -0,0 +1,292 @@

> +/** @file

> +  Secondary System Description Table (SSDT) for Synquacer PCIe RCs

> +

> +  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>

> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>

> +

> +  This program and the accompanying materials

> +  are licensed and made available under the terms and conditions of the BSD License

> +  which accompanies this distribution.  The full text of the license may be found at

> +  http://opensource.org/licenses/bsd-license.php

> +

> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +

> +**/

> +

> +#include <Platform/Pcie.h>

> +

> +#include "AcpiTables.h"

> +

> +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {

> +  Scope(_SB) {

> +    //

> +    // PCI Root Complex

> +    //

> +    Device(PCI0)

> +    {

> +        Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge

> +        Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge

> +        Name(_SEG, Zero)                // PCI Segment Group number

> +        Name(_BBN, Zero)                // PCI Base Bus Number

> +        Name(_CCA, 1)                   // Cache Coherency Attribute

> +

> +        // PCI Routing Table

> +        Name(_PRT, Package() {

> +            Package () { 0xFFFF, 0, Zero, 222 },   // INTA

> +            Package () { 0xFFFF, 1, Zero, 222 },   // INTB

> +            Package () { 0xFFFF, 2, Zero, 222 },   // INTC

> +            Package () { 0xFFFF, 3, Zero, 222 },   // INTD

> +        })

> +        // Root complex resources

> +        Method (_CRS, 0, Serialized) {

> +            Name (RBUF, ResourceTemplate () {

> +                WordBusNumber ( // Bus numbers assigned to this root

> +                    ResourceProducer,

> +                    MinFixed, MaxFixed, PosDecode,

> +                    0,                              // AddressGranularity

> +                    SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMinimum - Minimum Bus Number

> +                    SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMaximum - Maximum Bus Number

> +                    0,                              // AddressTranslation - Set to 0

> +                    1                               // RangeLength - Number of Busses

> +                )

> +

> +                DWordMemory ( // 32-bit BAR Windows

> +                    ResourceProducer, PosDecode,

> +                    MinFixed, MaxFixed,

> +                    Cacheable, ReadWrite,

> +                    0x00000000,                         // Granularity

> +                    SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address

> +                    SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address

> +                    0x00000000,                         // Translate

> +                    SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length

> +                )

> +

> +                QWordMemory ( // 64-bit BAR Windows

> +                    ResourceProducer, PosDecode,

> +                    MinFixed, MaxFixed,

> +                    Cacheable, ReadWrite,

> +                    0x00000000,                         // Granularity

> +                    SYNQUACER_PCI_SEG0_MMIO64_MIN,      // Min Base Address

> +                    SYNQUACER_PCI_SEG0_MMIO64_MAX,      // Max Base Address

> +                    0x00000000,                         // Translate

> +                    SYNQUACER_PCI_SEG0_MMIO64_SIZE      // Length

> +                )

> +

> +                DWordIo ( // IO window

> +                    ResourceProducer,

> +                    MinFixed,

> +                    MaxFixed,

> +                    PosDecode,

> +                    EntireRange,

> +                    0x00000000,                         // Granularity

> +                    SYNQUACER_PCI_SEG0_PORTIO_MIN,      // Min Base Address

> +                    SYNQUACER_PCI_SEG0_PORTIO_MAX,      // Max Base Address

> +                    SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,  // Translate

> +                    SYNQUACER_PCI_SEG0_PORTIO_SIZE,     // Length

> +                    ,

> +                    ,

> +                    ,

> +                    TypeTranslation

> +                )

> +            }) // Name(RBUF)

> +

> +            Return (RBUF)

> +        } // Method(_CRS)

> +

> +        Device (RES0)

> +        {

> +            Name (_HID, "PNP0C02")

> +            Name (_CRS, ResourceTemplate ()

> +            {

> +                Memory32Fixed (ReadWrite,

> +                               SYNQUACER_PCI_SEG0_CONFIG_BASE,

> +                               SYNQUACER_PCI_SEG0_CONFIG_SIZE)

> +            })

> +        }

> +

> +        //

> +        // OS Control Handoff

> +        //

> +        Name(SUPP, Zero) // PCI _OSC Support Field value

> +        Name(CTRL, Zero) // PCI _OSC Control Field value

> +

> +        /*

> +      See [1] 6.2.10, [2] 4.5

> +        */

> +        Method(_OSC,4) {

> +            // Check for proper UUID

> +            If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {

> +                // Create DWord-adressable fields from the Capabilities Buffer

> +                CreateDWordField(Arg3,0,CDW1)

> +                CreateDWordField(Arg3,4,CDW2)

> +                CreateDWordField(Arg3,8,CDW3)

> +

> +                // Save Capabilities DWord2 & 3

> +                Store(CDW2,SUPP)

> +                Store(CDW3,CTRL)

> +

> +                // Only allow native hot plug control if OS supports:

> +                // * ASPM

> +                // * Clock PM

> +                // * MSI/MSI-X

> +                If(LNotEqual(And(SUPP, 0x16), 0x16)) {

> +                    And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)

> +                }

> +

> +                // Always allow native PME, AER (no dependencies)

> +

> +                // Never allow SHPC (no SHPC controller in this system)

> +                And(CTRL,0x1D,CTRL)

> +

> +                If(LNotEqual(Arg1,One)) {    // Unknown revision

> +                    Or(CDW1,0x08,CDW1)

> +                }

> +

> +                If(LNotEqual(CDW3,CTRL)) {    // Capabilities bits were masked

> +                    Or(CDW1,0x10,CDW1)

> +                }

> +                // Update DWORD3 in the buffer

> +                Store(CTRL,CDW3)

> +                Return(Arg3)

> +            } Else {

> +                Or(CDW1,4,CDW1) // Unrecognized UUID

> +                Return(Arg3)

> +            }

> +        } // End _OSC

> +    } // PCI0

> +

> +    Device(PCI1)

> +    {

> +        Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge

> +        Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge

> +        Name(_SEG, 1)                   // PCI Segment Group number

> +        Name(_BBN, Zero)                // PCI Base Bus Number

> +        Name(_CCA, 1)                   // Cache Coherency Attribute

> +

> +        // PCI Routing Table

> +        Name(_PRT, Package() {

> +            Package () { 0xFFFF, 0, Zero, 214 },   // INTA

> +            Package () { 0xFFFF, 1, Zero, 214 },   // INTB

> +            Package () { 0xFFFF, 2, Zero, 214 },   // INTC

> +            Package () { 0xFFFF, 3, Zero, 214 },   // INTD

> +        })

> +        // Root complex resources

> +        Method (_CRS, 0, Serialized) {

> +            Name (RBUF, ResourceTemplate () {

> +                WordBusNumber ( // Bus numbers assigned to this root

> +                    ResourceProducer,

> +                    MinFixed, MaxFixed, PosDecode,

> +                    0,                              // AddressGranularity

> +                    SYNQUACER_PCI_SEG1_BUSNUM_MIN,  // AddressMinimum - Minimum Bus Number

> +                    SYNQUACER_PCI_SEG1_BUSNUM_MIN,  // AddressMaximum - Maximum Bus Number

> +                    0,                              // AddressTranslation - Set to 0

> +                    1                               // RangeLength - Number of Busses

> +                )

> +

> +                DWordMemory ( // 32-bit BAR Windows

> +                    ResourceProducer, PosDecode,

> +                    MinFixed, MaxFixed,

> +                    Cacheable, ReadWrite,

> +                    0x00000000,                         // Granularity

> +                    SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address

> +                    SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address

> +                    0x00000000,                         // Translate

> +                    SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length

> +                )

> +

> +                QWordMemory ( // 64-bit BAR Windows

> +                    ResourceProducer, PosDecode,

> +                    MinFixed, MaxFixed,

> +                    Cacheable, ReadWrite,

> +                    0x00000000,                         // Granularity

> +                    SYNQUACER_PCI_SEG1_MMIO64_MIN,      // Min Base Address

> +                    SYNQUACER_PCI_SEG1_MMIO64_MAX,      // Max Base Address

> +                    0x00000000,                         // Translate

> +                    SYNQUACER_PCI_SEG1_MMIO64_SIZE      // Length

> +                )

> +

> +                DWordIo ( // IO window

> +                    ResourceProducer,

> +                    MinFixed,

> +                    MaxFixed,

> +                    PosDecode,

> +                    EntireRange,

> +                    0x00000000,                         // Granularity

> +                    SYNQUACER_PCI_SEG1_PORTIO_MIN,      // Min Base Address

> +                    SYNQUACER_PCI_SEG1_PORTIO_MAX,      // Max Base Address

> +                    SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,  // Translate

> +                    SYNQUACER_PCI_SEG1_PORTIO_SIZE,     // Length

> +                    ,

> +                    ,

> +                    ,

> +                    TypeTranslation

> +                )

> +            }) // Name(RBUF)

> +

> +            Return (RBUF)

> +        } // Method(_CRS)

> +

> +        Device (RES0)

> +        {

> +            Name (_HID, "PNP0C02")

> +            Name (_CRS, ResourceTemplate ()

> +            {

> +                Memory32Fixed (ReadWrite,

> +                               SYNQUACER_PCI_SEG1_CONFIG_BASE,

> +                               SYNQUACER_PCI_SEG1_CONFIG_SIZE)

> +            })

> +        }

> +

> +        //

> +        // OS Control Handoff

> +        //

> +        Name(SUPP, Zero) // PCI _OSC Support Field value

> +        Name(CTRL, Zero) // PCI _OSC Control Field value

> +

> +        /*

> +      See [1] 6.2.10, [2] 4.5

> +        */

> +        Method(_OSC,4) {

> +            // Check for proper UUID

> +            If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {

> +                // Create DWord-adressable fields from the Capabilities Buffer

> +                CreateDWordField(Arg3,0,CDW1)

> +                CreateDWordField(Arg3,4,CDW2)

> +                CreateDWordField(Arg3,8,CDW3)

> +

> +                // Save Capabilities DWord2 & 3

> +                Store(CDW2,SUPP)

> +                Store(CDW3,CTRL)

> +

> +                // Only allow native hot plug control if OS supports:

> +                // * ASPM

> +                // * Clock PM

> +                // * MSI/MSI-X

> +                If(LNotEqual(And(SUPP, 0x16), 0x16)) {

> +                    And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)

> +                }

> +

> +                // Always allow native PME, AER (no dependencies)

> +

> +                // Never allow SHPC (no SHPC controller in this system)

> +                And(CTRL,0x1D,CTRL)

> +

> +                If(LNotEqual(Arg1,One)) {    // Unknown revision

> +                    Or(CDW1,0x08,CDW1)

> +                }

> +

> +                If(LNotEqual(CDW3,CTRL)) {    // Capabilities bits were masked

> +                    Or(CDW1,0x10,CDW1)

> +                }

> +                // Update DWORD3 in the buffer

> +                Store(CTRL,CDW3)

> +                Return(Arg3)

> +            } Else {

> +                Or(CDW1,4,CDW1) // Unrecognized UUID

> +                Return(Arg3)

> +            }

> +        } // End _OSC

> +    } // PCI0

> +  }

> +}

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h

> new file mode 100644

> index 000000000000..73fe4f5caa3e

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h

> @@ -0,0 +1,58 @@

> +/** @file

> +*

> +*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.

> +*  Copyright (c) 2017, Linaro Limited. All rights reserved.

> +*

> +*  This program and the accompanying materials

> +*  are licensed and made available under the terms and conditions of the BSD License

> +*  which accompanies this distribution.  The full text of the license may be found at

> +*  http://opensource.org/licenses/bsd-license.php

> +*

> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +*

> +**/

> +

> +#ifndef __ACPITABLES_H__

> +#define __ACPITABLES_H__

> +

> +//

> +// ACPI table information used to initialize tables.

> +//

> +#define EFI_ACPI_OEM_ID           'L','I','N','A','R','O'   // OEMID 6 bytes long

> +#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('S','Y','N','Q','U','A','C','R') // OEM table id 8 bytes long

> +#define EFI_ACPI_OEM_REVISION     0x20170802

> +#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('L','N','R','O')


The Linaro IDs here - are they to be considered temporary until
Socionext get their own?

> +#define EFI_ACPI_CREATOR_REVISION 0x00000001

> +

> +// A macro to initialise the common header part of EFI ACPI tables as defined by

> +// EFI_ACPI_DESCRIPTION_HEADER structure.

> +#define __ACPI_HEADER(Signature, Type, Revision) {                \

> +    Signature,                      /* UINT32  Signature */       \

> +    sizeof (Type),                  /* UINT32  Length */          \

> +    Revision,                       /* UINT8   Revision */        \

> +    0,                              /* UINT8   Checksum */        \

> +    { EFI_ACPI_OEM_ID },            /* UINT8   OemId[6] */        \

> +    EFI_ACPI_OEM_TABLE_ID,          /* UINT64  OemTableId */      \

> +    EFI_ACPI_OEM_REVISION,          /* UINT32  OemRevision */     \

> +    EFI_ACPI_CREATOR_ID,            /* UINT32  CreatorId */       \

> +    EFI_ACPI_CREATOR_REVISION       /* UINT32  CreatorRevision */ \

> +  }

> +

> +#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \

> +  { \

> +    EFI_ACPI_6_0_GICR, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), 0, RedisRegionAddr, RedisDiscLength \

> +  }

> +

> +#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \

> +  { EFI_ACPI_6_0_GIC_ITS, sizeof(EFI_ACPI_6_0_GIC_ITS_STRUCTURE), 0, Id, PhysAddress, 0 }

> +

> +#define EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhysicalAddress,                  \

> +    ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags)                                 \

> +  {                                                                                                     \

> +    EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \

> +    EFI_ACPI_RESERVED_WORD, RefreshFramePhysicalAddress, ControlFramePhysicalAddress,                   \

> +    WatchdogTimerGSIV, WatchdogTimerFlags                                                               \

> +  }

> +

> +#endif

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf

> new file mode 100644

> index 000000000000..f390797b9d4f

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf

> @@ -0,0 +1,58 @@

> +## @file

> +#

> +#  ACPI table data and ASL sources required to boot the platform.

> +#

> +#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.

> +#  Copyright (c) 2017, Linaro Ltd. All rights reserved.

> +#

> +#  This program and the accompanying materials

> +#  are licensed and made available under the terms and conditions of the BSD License

> +#  which accompanies this distribution.  The full text of the license may be found at

> +#  http://opensource.org/licenses/bsd-license.php

> +#

> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +#

> +##

> +

> +[Defines]

> +  INF_VERSION                    = 0x00010005


Bump.

> +  BASE_NAME                      = SynquacerAcpiTables

> +  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD

> +  MODULE_TYPE                    = USER_DEFINED

> +  VERSION_STRING                 = 1.0

> +

> +[Sources]

> +  AcpiTables.h

> +  AcpiSsdtRootPci.asl

> +  Dsdt.asl

> +  Fadt.aslc

> +  Gtdt.aslc

> +  Iort.aslc

> +  Madt.aslc

> +  Mcfg.aslc

> +  Spcr.aslc

> +

> +[Packages]

> +  ArmPlatformPkg/ArmPlatformPkg.dec

> +  ArmPkg/ArmPkg.dec

> +  EmbeddedPkg/EmbeddedPkg.dec

> +  MdePkg/MdePkg.dec

> +  MdeModulePkg/MdeModulePkg.dec

> +  Silicon/Socionext/Synquacer/Synquacer.dec

> +

> +[FixedPcd]

> +  gArmPlatformTokenSpaceGuid.PcdClusterCount

> +  gArmPlatformTokenSpaceGuid.PcdCoreCount

> +  gArmTokenSpaceGuid.PcdGicDistributorBase

> +  gArmTokenSpaceGuid.PcdGicRedistributorsBase

> +

> +  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum

> +  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum

> +  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum

> +  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum

> +

> +  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase

> +  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase

> +

> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl

> new file mode 100644

> index 000000000000..dc32a34ccfa2

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl

> @@ -0,0 +1,168 @@

> +/** @file

> +  Differentiated System Description Table Fields (DSDT)

> +

> +  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>

> +    This program and the accompanying materials

> +  are licensed and made available under the terms and conditions of the BSD License

> +  which accompanies this distribution.  The full text of the license may be found at

> +  http://opensource.org/licenses/bsd-license.php

> +

> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +

> +**/

> +

> +#include "AcpiTables.h"

> +

> +#include <Platform/MemoryMap.h>

> +

> +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {

> +  Scope(_SB) {

> +    //

> +    // A53x4 Processor declaration

> +    //

> +    Device(CP00) { // A53-0: Cluster 0, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 0)

> +    }

> +    Device(CP01) { // A53-0: Cluster 0, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 1)

> +    }

> +

> +    Device(CP04) { // A53-0: Cluster 1, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 2)

> +    }

> +    Device(CP05) { // A53-0: Cluster 1, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 3)

> +    }


Is keeping 4 device names per cluster (so giving holes here) mandated
by ACPI?

> +

> +    Device(CP08) { // A53-0: Cluster 2, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 4)

> +    }

> +    Device(CP09) { // A53-0: Cluster 2, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 5)

> +    }

> +

> +    Device(CP12) { // A53-0: Cluster 3, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 6)

> +    }

> +    Device(CP13) { // A53-0: Cluster 3, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 7)

> +    }

> +

> +    Device(CP16) { // A53-0: Cluster 4, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 8)

> +    }

> +    Device(CP17) { // A53-0: Cluster 4, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 9)

> +    }

> +

> +    Device(CP20) { // A53-0: Cluster 5, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 10)

> +    }

> +    Device(CP21) { // A53-0: Cluster 5, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 11)

> +    }

> +

> +    Device(CP24) { // A53-0: Cluster 6, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 12)

> +    }

> +    Device(CP25) { // A53-0: Cluster 6, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 13)

> +    }

> +

> +    Device(CP28) { // A53-0: Cluster 7, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 14)

> +    }

> +    Device(CP29) { // A53-0: Cluster 7, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 15)

> +    }

> +

> +    Device(CP32) { // A53-0: Cluster 8, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 16)

> +    }

> +    Device(CP33) { // A53-0: Cluster 8, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 17)

> +    }

> +

> +    Device(CP36) { // A53-0: Cluster 9, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 18)

> +    }

> +    Device(CP37) { // A53-0: Cluster 9, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 19)

> +    }

> +

> +    Device(CP40) { // A53-0: Cluster 10, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 20)

> +    }

> +    Device(CP41) { // A53-0: Cluster 10, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 21)

> +    }

> +

> +    Device(CP44) { // A53-0: Cluster 11, Cpu 0

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 22)

> +    }

> +    Device(CP45) { // A53-0: Cluster 11, Cpu 1

> +      Name(_HID, "ACPI0007")

> +      Name(_UID, 23)

> +    }

> +

> +    // UART PL011

> +    Device(COM0) {

> +      Name(_HID, "ARMH0011")

> +      Name(_CID, "PL011")

> +      Name(_UID, Zero)

> +      Name(_CRS, ResourceTemplate() {

> +        Memory32Fixed(ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000)

> +        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 }

> +      })

> +    }

> +

> +    Device(NET0) {

> +      Name(_HID, "SCX0001")

> +      Name(_UID, Zero)

> +      Name(_CCA, Zero)

> +      Name(_CRS, ResourceTemplate() {

> +        Memory32Fixed(ReadWrite, SYNQUACER_NETSEC_BASE,

> +                                 SYNQUACER_NETSEC_BASE_SZ)

> +        Memory32Fixed(ReadWrite, SYNQUACER_EEPROM_BASE,

> +                                 SYNQUACER_EEPROM_BASE_SZ)

> +        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 208 }

> +      })

> +

> +      Name (_DSD, Package ()  // _DSD: Device-Specific Data

> +      {

> +        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),

> +        Package () {

> +          Package (2) { "phy-mode", "rgmii" },

> +          Package (2) { "phy-channel", 0x1 },

> +          Package (2) { "max-speed", 1000 },

> +          Package (2) { "max-frame-size", 9000 },

> +          Package (2) { "socionext,phy-clock-frequency", 125000000 },

> +        }

> +      })

> +    }

> +  } // Scope(_SB)

> +}

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc

> new file mode 100644

> index 000000000000..26e4e0fc8964

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc

> @@ -0,0 +1,88 @@

> +/** @file

> +*  Fixed ACPI Description Table (FADT)

> +*

> +*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.

> +*

> +*  This program and the accompanying materials

> +*  are licensed and made available under the terms and conditions of the BSD License

> +*  which accompanies this distribution.  The full text of the license may be found at

> +*  http://opensource.org/licenses/bsd-license.php

> +*

> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +*

> +**/

> +

> +#include <Library/AcpiLib.h>

> +#include <IndustryStandard/Acpi.h>

> +

> +#include "AcpiTables.h"

> +

> +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {

> +  __ACPI_HEADER (

> +    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,

> +    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,

> +    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION

> +  ),

> +  0,                                                                        // UINT32     FirmwareCtrl

> +  0,                                                                        // UINT32     Dsdt

> +  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0

> +  EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER,                                // UINT8      PreferredPmProfile

> +  0,                                                                        // UINT16     SciInt

> +  0,                                                                        // UINT32     SmiCmd

> +  0,                                                                        // UINT8      AcpiEnable

> +  0,                                                                        // UINT8      AcpiDisable

> +  0,                                                                        // UINT8      S4BiosReq

> +  0,                                                                        // UINT8      PstateCnt

> +  0,                                                                        // UINT32     Pm1aEvtBlk

> +  0,                                                                        // UINT32     Pm1bEvtBlk

> +  0,                                                                        // UINT32     Pm1aCntBlk

> +  0,                                                                        // UINT32     Pm1bCntBlk

> +  0,                                                                        // UINT32     Pm2CntBlk

> +  0,                                                                        // UINT32     PmTmrBlk

> +  0,                                                                        // UINT32     Gpe0Blk

> +  0,                                                                        // UINT32     Gpe1Blk

> +  0,                                                                        // UINT8      Pm1EvtLen

> +  0,                                                                        // UINT8      Pm1CntLen

> +  0,                                                                        // UINT8      Pm2CntLen

> +  0,                                                                        // UINT8      PmTmrLen

> +  0,                                                                        // UINT8      Gpe0BlkLen

> +  0,                                                                        // UINT8      Gpe1BlkLen

> +  0,                                                                        // UINT8      Gpe1Base

> +  0,                                                                        // UINT8      CstCnt

> +  0,                                                                        // UINT16     PLvl2Lat

> +  0,                                                                        // UINT16     PLvl3Lat

> +  0,                                                                        // UINT16     FlushSize

> +  0,                                                                        // UINT16     FlushStride

> +  0,                                                                        // UINT8      DutyOffset

> +  0,                                                                        // UINT8      DutyWidth

> +  0,                                                                        // UINT8      DayAlrm

> +  0,                                                                        // UINT8      MonAlrm

> +  0,                                                                        // UINT8      Century

> +  0,                                                                        // UINT16     IaPcBootArch

> +  0,                                                                        // UINT8      Reserved1

> +  EFI_ACPI_6_0_HW_REDUCED_ACPI | EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  ResetReg

> +  0,                                                                        // UINT8      ResetValue

> +  EFI_ACPI_6_0_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags

> +  EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision

> +  0,                                                                        // UINT64     XFirmwareCtrl

> +  0,                                                                        // UINT64     XDsdt

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg

> +  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg

> +  0                                                                         // UINT64     HypervisorVendorIdentity;

> +};

> +

> +//

> +// Reference the table being generated to prevent the optimizer from removing the

> +// data structure from the executable

> +//

> +VOID* CONST ReferenceAcpiTable = &Fadt;

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc

> new file mode 100644

> index 000000000000..f22c27f05454

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc

> @@ -0,0 +1,98 @@

> +/** @file

> +*  Generic Timer Description Table (GTDT)

> +*

> +*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.

> +*  Copyright (c) 2017, Linaro Limited. All rights reserved.

> +*

> +*  This program and the accompanying materials

> +*  are licensed and made available under the terms and conditions of the BSD License

> +*  which accompanies this distribution.  The full text of the license may be found at

> +*  http://opensource.org/licenses/bsd-license.php

> +*

> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +*

> +**/

> +

> +#include <Library/AcpiLib.h>

> +#include <Library/PcdLib.h>

> +#include <IndustryStandard/Acpi.h>

> +

> +#include "AcpiTables.h"

> +

> +#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT

> +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0

> +#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE

> +#define GTDT_GLOBAL_FLAGS_LEVEL       0

> +

> +#define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)

> +#define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF

> +

> +#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE

> +#define GTDT_TIMER_LEVEL_TRIGGERED  0

> +#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY

> +#define GTDT_TIMER_ACTIVE_HIGH      0

> +

> +#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)

> +

> +#pragma pack (1)

> +

> +typedef struct {

> +  EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;

> +  EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE                  TimerBase;

> +  EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE            TimerFrame;

> +  EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdog;

> +} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES;

> +

> +#pragma pack ()

> +

> +EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {

> +  {

> +    __ACPI_HEADER(

> +      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,

> +      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES,

> +      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION

> +    ),

> +    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress

> +    0,                                            // UINT32  Reserved

> +    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV

> +    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags

> +    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV

> +    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags

> +    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV

> +    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags

> +    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV

> +    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags

> +    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress

> +    2,                                            // UINT32  PlatformTimerCount

> +    sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset

> +  },

> +  {

> +    EFI_ACPI_6_0_GTDT_GT_BLOCK,                                 // UINT8  Type

> +    sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) +

> +    sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE),        // UINT16 Length

> +    EFI_ACPI_RESERVED_BYTE,                                     // UINT8  Reserved

> +    0x2A810000,                                                 // UINT64 CntCtlBase

> +    1,                                                          // UINT32 GTBlockTimerCount

> +    sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE)               // UINT32 GTBlockTimerOffset

> +  },

> +  {

> +    0,                                                          // UINT8  GTFrameNumber

> +    {0, 0, 0},                                                  // UINT8  Reserved[3]

> +    0x2A830000,                                                 // UINT64 CntBaseX

> +    0xFFFFFFFFFFFFFFFF,                                         // UINT64 CntEL0BaseX

> +    92,                                                         // UINT32 GTxPhysicalTimerGSIV

> +    GTDT_TIMER_LEVEL_TRIGGERED | GTDT_TIMER_ACTIVE_HIGH,        // UINT32 GTxPhysicalTimerFlags

> +    0,                                                          // UINT32 GTxVirtualTimerGSIV

> +    0,                                                          // UINT32 GTxVirtualTimerFlags

> +    EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY // UINT32 GTxCommonFlags

> +  },

> +  EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(

> +    FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, 0),

> +};

> +

> +//

> +// Reference the table being generated to prevent the optimizer from removing the

> +// data structure from the executable

> +//

> +VOID* CONST ReferenceAcpiTable = &Gtdt;

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc

> new file mode 100644

> index 000000000000..bbb425f1f808

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc

> @@ -0,0 +1,164 @@

> +/** @file

> +

> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>

> +

> +  This program and the accompanying materials

> +  are licensed and made available under the terms and conditions of the BSD License

> +  which accompanies this distribution.  The full text of the license may be found at

> +  http://opensource.org/licenses/bsd-license.php

> +

> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +

> +**/

> +

> +#include <IndustryStandard/IoRemappingTable.h>

> +

> +#include "AcpiTables.h"

> +

> +#define FIELD_OFFSET(type, name)            __builtin_offsetof(type, name)

> +

> +#pragma pack(1)

> +typedef struct {

> +  EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE        Node;

> +  UINT32                                    Identifiers[1];

> +} SYNQUACER_ITS_NODE;

> +

> +typedef struct {

> +  EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE       Node;

> +  EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT        Context[2];

> +  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE        RcIdMapping[1];

> +} SYNQUACER_SMMU_NODE;

> +

> +typedef struct {

> +  EFI_ACPI_6_0_IO_REMAPPING_RC_NODE         Node;

> +  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE        RcIdMapping[1];

> +} SYNQUACER_RC_NODE;

> +

> +typedef struct {

> +  EFI_ACPI_6_0_IO_REMAPPING_TABLE           Iort;

> +  SYNQUACER_ITS_NODE                        ItsNode;

> +  //SYNQUACER_SMMU_NODE                       Smmu;

> +  SYNQUACER_RC_NODE                         RcNode[2];

> +} SYNQUACER_IO_REMAPPING_STRUCTURE;

> +

> +#define __SYNQUACER_SMMU_NODE(Base, Size, Irq, NumIds)      \

> +  {                                                         \

> +    {                                                       \

> +      EFI_ACPI_IORT_TYPE_SMMUv1v2,                          \

> +      sizeof(SYNQUACER_SMMU_NODE),                          \

> +      0x0,                                                  \

> +      0x0,                                                  \

> +      NumIds,                                               \

> +      FIELD_OFFSET(SYNQUACER_SMMU_NODE, RcIdMapping),       \

> +    },                                                      \

> +    Base,                                                   \

> +    Size,                                                   \

> +    EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500,                    \

> +    0,                                                      \

> +    FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE,       \

> +                 SMMU_NSgIrpt),                             \

> +    0x2,                                                    \

> +    sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE),            \

> +    0x0,                                                    \

> +    0x0,                                                    \

> +    Irq,                                                    \

> +    EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL,                  \

> +    0x0,                                                    \

> +    0x0,                                                    \

> +  }, {                                                      \

> +    {                                                       \

> +      Irq,                                                  \

> +      EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL,                \

> +    },                                                      \

> +    {                                                       \

> +      Irq,                                                  \

> +      EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL,                \

> +    },                                                      \

> +  }

> +

> +#define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags)    \

> +  {                                                         \

> +    In,                                                     \

> +    Num,                                                    \

> +    Out,                                                    \

> +    FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, Ref),    \

> +    Flags                                                   \

> +  }

> +

> +STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {

> +  {

> +    __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,

> +                  SYNQUACER_IO_REMAPPING_STRUCTURE,

> +                  EFI_ACPI_IO_REMAPPING_TABLE_REVISION),

> +    3,                                              // NumNodes

> +    sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE),        // NodeOffset

> +    0                                               // Reserved

> +  }, {

> +    // ItsNode

> +    {

> +      {

> +        EFI_ACPI_IORT_TYPE_ITS_GROUP,                       // Type

> +        sizeof(SYNQUACER_ITS_NODE),                         // Length

> +        0x0,                                                // Revision

> +        0x0,                                                // Reserved

> +        0x0,                                                // NumIdMappings

> +        0x0,                                                // IdReference

> +      },

> +      1,

> +    }, {

> +      0x0

> +    },

> +  }, {

> +//     __SYNQUACER_SMMU_NODE(0x582C0000, 0x10000, 234, 1),

> +//     { __SYNQUACER_ID_MAPPING(0x200, 0x0, 0x0, ItsNode, 0x0), }

> +//  }, {

> +    // PciRcNode

> +    {

> +      {

> +        {

> +          EFI_ACPI_IORT_TYPE_ROOT_COMPLEX,                    // Type

> +          sizeof(SYNQUACER_RC_NODE),                          // Length

> +          0x0,                                                // Revision

> +          0x0,                                                // Reserved

> +          0x1,                                                // NumIdMappings

> +          FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping),       // IdReference

> +        },

> +        EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,                    // CacheCoherent

> +        0x0,                                                  // AllocationHints

> +        0x0,                                                  // Reserved

> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |

> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS,                  // MemoryAccessFlags

> +        EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,           // AtsAttribute

> +        0x0,                                                  // PciSegmentNumber

> +      }, {

> +        __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),

> +      },

> +    }, {

> +      // PciRcNode

> +      {

> +        {

> +          EFI_ACPI_IORT_TYPE_ROOT_COMPLEX,                    // Type

> +          sizeof(SYNQUACER_RC_NODE),                          // Length

> +          0x0,                                                // Revision

> +          0x0,                                                // Reserved

> +          0x1,                                                // NumIdMappings

> +          FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping),       // IdReference

> +        },

> +        EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,                    // CacheCoherent

> +        0x0,                                                  // AllocationHints

> +        0x0,                                                  // Reserved

> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |

> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS,                  // MemoryAccessFlags

> +        EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,           // AtsAttribute

> +        0x1,                                                  // PciSegmentNumber

> +      }, {

> +        __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),

> +      }

> +    }

> +  }

> +};

> +

> +#pragma pack()

> +

> +VOID* CONST ReferenceAcpiTable = &Iort;

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc

> new file mode 100644

> index 000000000000..a8c27dcf8923

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc

> @@ -0,0 +1,152 @@

> +/** @file

> +*  Multiple APIC Description Table (MADT)

> +*

> +*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.

> +*

> +*  This program and the accompanying materials

> +*  are licensed and made available under the terms and conditions of the BSD License

> +*  which accompanies this distribution.  The full text of the license may be found at

> +*  http://opensource.org/licenses/bsd-license.php

> +*

> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +*

> +**/

> +

> +#include <Library/AcpiLib.h>

> +#include <Library/ArmLib.h>

> +#include <Library/PcdLib.h>

> +#include <IndustryStandard/Acpi.h>

> +

> +#include "AcpiTables.h"

> +

> +//

> +// Multiple APIC Description Table

> +//

> +#pragma pack (1)

> +

> +typedef struct {

> +  EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;

> +  EFI_ACPI_6_0_GIC_STRUCTURE                            GicInterfaces[FixedPcdGet32 (PcdClusterCount) * FixedPcdGet32 (PcdCoreCount)];

> +  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;

> +  EFI_ACPI_6_0_GICR_STRUCTURE                           GicRedistributor;

> +  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                        GicIts;

> +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE;

> +

> +#pragma pack ()

> +

> +EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {

> +  {

> +    __ACPI_HEADER (

> +      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,

> +      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE,

> +      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION

> +    ),

> +    //

> +    // MADT specific fields

> +    //

> +    0, // LocalApicAddress

> +    0, // Flags

> +  },

> +  {

> +    // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, GicBase, GicVBase,

> +    //                                          GicHBase, GsivId, GicRBase)

> +    // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of

> +    //       ACPI v6.0).

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0

> +        0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-1

> +        0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-2

> +        0, 2, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-3

> +        0, 3, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-4

> +        0, 4, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-5

> +        0, 5, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-6

> +        0, 6, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-7

> +        0, 7, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-8

> +        0, 8, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-9

> +        0, 9, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-10

> +        0, 10, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-11

> +        0, 11, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-12

> +        0, 12, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-13

> +        0, 13, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-14

> +        0, 14, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-15

> +        0, 15, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-16

> +        0, 16, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-17

> +        0, 17, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-18

> +        0, 18, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-19

> +        0, 19, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-20

> +        0, 20, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-21

> +        0, 21, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-22

> +        0, 22, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-23

> +        0, 23, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),

> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

> +  },

> +  // GIC Distributor Entry

> +  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3),

> +  // GIC Redistributor

> +  EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), 0x300000),

> +  // GIC ITS

> +  EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000)

> +};

> +

> +//

> +// Reference the table being generated to prevent the optimizer from removing the

> +// data structure from the executable

> +//

> +VOID* CONST ReferenceAcpiTable = &Madt;

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc

> new file mode 100644

> index 000000000000..00df5f181de3

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc

> @@ -0,0 +1,63 @@

> +/** @file

> +

> +  ACPI Memory mapped configuration space base address Description Table (MCFG).

> +  Implementation based on PCI Firmware Specification Revision 3.0 final draft,

> +  downloadable at http://www.pcisig.com/home

> +

> +  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.

> +  Copyright (c) 2017, Linaro Limited. All rights reserved.

> +

> +  This program and the accompanying materials are licensed and

> +  made available under the terms and conditions of the BSD License

> +  which accompanies this distribution.  The full text of the

> +  license may be found at http://opensource.org/licenses/bsd-license.php

> +

> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +

> +**/

> +

> +#include <IndustryStandard/Acpi61.h>

> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>

> +#include <Platform/Pcie.h>

> +

> +#include "AcpiTables.h"

> +

> +#pragma pack(push, 1)

> +

> +typedef struct {

> +  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;

> +  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];

> +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;

> +

> +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {

> +  {

> +    __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,

> +    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,

> +    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),

> +    EFI_ACPI_RESERVED_QWORD

> +  },

> +  {

> +    {

> +      SYNQUACER_PCI_SEG0_CONFIG_BASE | 0x8000,

> +      0,

> +      SYNQUACER_PCI_SEG0_BUSNUM_MIN,

> +      SYNQUACER_PCI_SEG0_BUSNUM_MIN,

> +      EFI_ACPI_RESERVED_DWORD

> +    }, {

> +      SYNQUACER_PCI_SEG1_CONFIG_BASE | 0x8000,

> +      1,

> +      SYNQUACER_PCI_SEG1_BUSNUM_MIN,

> +      SYNQUACER_PCI_SEG1_BUSNUM_MIN,

> +      EFI_ACPI_RESERVED_DWORD

> +    }

> +  }

> +};

> +

> +#pragma pack(pop)

> +

> +//

> +// Reference the table being generated to prevent the optimizer from removing the

> +// data structure from the executable

> +//

> +VOID* CONST ReferenceAcpiTable = &Mcfg;

> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc

> new file mode 100644

> index 000000000000..f51475e5c6a2

> --- /dev/null

> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc

> @@ -0,0 +1,127 @@

> +/** @file

> +

> +  Serial Port Console Redirection Table

> +  (c) 2000 - 2014 Microsoft Corporation. All rights reserved.

> +  http://go.microsoft.com/fwlink/?linkid=403368

> +

> +  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.

> +

> +  This program and the accompanying materials

> +  are licensed and made available under the terms and conditions of the BSD License

> +  which accompanies this distribution.  The full text of the license may be found at

> +  http://opensource.org/licenses/bsd-license.php

> +

> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

> +

> +**/

> +

> +#include <IndustryStandard/Acpi61.h>

> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>

> +

> +#include "AcpiTables.h"

> +

> +#pragma pack(push, 1)

> +

> +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {

> +  //

> +  // Header

> +  //

> +  __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,

> +                 EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,

> +                 2), /* New MS definition for PL011 support */


Umm, PL011 is defined as 0x0003 in my DBG2 version.
2 is ("reserved").

32-bit only SBSA UART and SBSA UART are 0x000d and 0x000e respectively.

/
    Leif

> +  //

> +  // InterfaceType

> +  //

> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,

> +  //

> +  // Reserved[3]

> +  //

> +  { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },

> +  //

> +  // BaseAddress

> +  //

> +  {

> +    EFI_ACPI_5_1_SYSTEM_MEMORY,

> +    32,

> +    0,

> +    EFI_ACPI_5_1_DWORD,

> +    FixedPcdGet32 (PcdSerialRegisterBase)

> +  },

> +  //

> +  // InterruptType

> +  //

> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,

> +  //

> +  // Irq

> +  //

> +  0,

> +  //

> +  // GlobalSystemInterrupt

> +  //

> +  95,

> +  //

> +  // BaudRate

> +  //

> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,

> +  //

> +  // Parity

> +  //

> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,

> +  //

> +  // StopBits

> +  //

> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,

> +  //

> +  // FlowControl

> +  //

> +  0,

> +  //

> +  // TerminalType

> +  //

> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,

> +  //

> +  // Language

> +  //

> +  EFI_ACPI_RESERVED_BYTE,

> +  //

> +  // PciDeviceId

> +  //

> +  0xFFFF,

> +  //

> +  // PciVendorId

> +  //

> +  0xFFFF,

> +  //

> +  // PciBusNumber

> +  //

> +  0x00,

> +  //

> +  // PciDeviceNumber

> +  //

> +  0x00,

> +  //

> +  // PciFunctionNumber

> +  //

> +  0x00,

> +  //

> +  // PciFlags

> +  //

> +  0,

> +  //

> +  // PciSegment

> +  //

> +  0,

> +  //

> +  // Reserved2

> +  //

> +  EFI_ACPI_RESERVED_DWORD

> +};

> +

> +#pragma pack(pop)

> +

> +//

> +// Reference the table being generated to prevent the optimizer from removing

> +// the data structure from the executable

> +//

> +VOID* CONST ReferenceAcpiTable = &Spcr;

> -- 

> 2.11.0

> 

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Patch

diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index 3d4fbc87e2fa..b2befd2480c4 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -475,3 +475,17 @@ 
     <LibraryClasses>
       DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
   }
+
+  #
+  # ACPI support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+    <LibraryClasses>
+      #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+
+    <PcdsFixedAtBuild>
+      # support ACPI v5.0 or later
+      gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+  }
+  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index bd06adf93b3c..35742ad5a347 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -183,6 +183,13 @@  READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
   INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
 
+  #
+  # ACPI support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
+
 [FV.FVMAIN_COMPACT]
 FvAlignment        = 8
 ERASE_POLARITY     = 1
@@ -329,3 +336,9 @@  READ_LOCK_STATUS   = TRUE
     UI        STRING="$(MODULE_NAME)" Optional
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
   }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
+    RAW ASL                |.aml
+  }
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
new file mode 100644
index 000000000000..f8d503d65ead
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
@@ -0,0 +1,292 @@ 
+/** @file
+  Secondary System Description Table (SSDT) for Synquacer PCIe RCs
+
+  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Platform/Pcie.h>
+
+#include "AcpiTables.h"
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
+  Scope(_SB) {
+    //
+    // PCI Root Complex
+    //
+    Device(PCI0)
+    {
+        Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge
+        Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge
+        Name(_SEG, Zero)                // PCI Segment Group number
+        Name(_BBN, Zero)                // PCI Base Bus Number
+        Name(_CCA, 1)                   // Cache Coherency Attribute
+
+        // PCI Routing Table
+        Name(_PRT, Package() {
+            Package () { 0xFFFF, 0, Zero, 222 },   // INTA
+            Package () { 0xFFFF, 1, Zero, 222 },   // INTB
+            Package () { 0xFFFF, 2, Zero, 222 },   // INTC
+            Package () { 0xFFFF, 3, Zero, 222 },   // INTD
+        })
+        // Root complex resources
+        Method (_CRS, 0, Serialized) {
+            Name (RBUF, ResourceTemplate () {
+                WordBusNumber ( // Bus numbers assigned to this root
+                    ResourceProducer,
+                    MinFixed, MaxFixed, PosDecode,
+                    0,                              // AddressGranularity
+                    SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMinimum - Minimum Bus Number
+                    SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMaximum - Maximum Bus Number
+                    0,                              // AddressTranslation - Set to 0
+                    1                               // RangeLength - Number of Busses
+                )
+
+                DWordMemory ( // 32-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length
+                )
+
+                QWordMemory ( // 64-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG0_MMIO64_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG0_MMIO64_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG0_MMIO64_SIZE      // Length
+                )
+
+                DWordIo ( // IO window
+                    ResourceProducer,
+                    MinFixed,
+                    MaxFixed,
+                    PosDecode,
+                    EntireRange,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG0_PORTIO_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG0_PORTIO_MAX,      // Max Base Address
+                    SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,  // Translate
+                    SYNQUACER_PCI_SEG0_PORTIO_SIZE,     // Length
+                    ,
+                    ,
+                    ,
+                    TypeTranslation
+                )
+            }) // Name(RBUF)
+
+            Return (RBUF)
+        } // Method(_CRS)
+
+        Device (RES0)
+        {
+            Name (_HID, "PNP0C02")
+            Name (_CRS, ResourceTemplate ()
+            {
+                Memory32Fixed (ReadWrite,
+                               SYNQUACER_PCI_SEG0_CONFIG_BASE,
+                               SYNQUACER_PCI_SEG0_CONFIG_SIZE)
+            })
+        }
+
+        //
+        // OS Control Handoff
+        //
+        Name(SUPP, Zero) // PCI _OSC Support Field value
+        Name(CTRL, Zero) // PCI _OSC Control Field value
+
+        /*
+      See [1] 6.2.10, [2] 4.5
+        */
+        Method(_OSC,4) {
+            // Check for proper UUID
+            If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+                // Create DWord-adressable fields from the Capabilities Buffer
+                CreateDWordField(Arg3,0,CDW1)
+                CreateDWordField(Arg3,4,CDW2)
+                CreateDWordField(Arg3,8,CDW3)
+
+                // Save Capabilities DWord2 & 3
+                Store(CDW2,SUPP)
+                Store(CDW3,CTRL)
+
+                // Only allow native hot plug control if OS supports:
+                // * ASPM
+                // * Clock PM
+                // * MSI/MSI-X
+                If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+                    And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+                }
+
+                // Always allow native PME, AER (no dependencies)
+
+                // Never allow SHPC (no SHPC controller in this system)
+                And(CTRL,0x1D,CTRL)
+
+                If(LNotEqual(Arg1,One)) {    // Unknown revision
+                    Or(CDW1,0x08,CDW1)
+                }
+
+                If(LNotEqual(CDW3,CTRL)) {    // Capabilities bits were masked
+                    Or(CDW1,0x10,CDW1)
+                }
+                // Update DWORD3 in the buffer
+                Store(CTRL,CDW3)
+                Return(Arg3)
+            } Else {
+                Or(CDW1,4,CDW1) // Unrecognized UUID
+                Return(Arg3)
+            }
+        } // End _OSC
+    } // PCI0
+
+    Device(PCI1)
+    {
+        Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge
+        Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge
+        Name(_SEG, 1)                   // PCI Segment Group number
+        Name(_BBN, Zero)                // PCI Base Bus Number
+        Name(_CCA, 1)                   // Cache Coherency Attribute
+
+        // PCI Routing Table
+        Name(_PRT, Package() {
+            Package () { 0xFFFF, 0, Zero, 214 },   // INTA
+            Package () { 0xFFFF, 1, Zero, 214 },   // INTB
+            Package () { 0xFFFF, 2, Zero, 214 },   // INTC
+            Package () { 0xFFFF, 3, Zero, 214 },   // INTD
+        })
+        // Root complex resources
+        Method (_CRS, 0, Serialized) {
+            Name (RBUF, ResourceTemplate () {
+                WordBusNumber ( // Bus numbers assigned to this root
+                    ResourceProducer,
+                    MinFixed, MaxFixed, PosDecode,
+                    0,                              // AddressGranularity
+                    SYNQUACER_PCI_SEG1_BUSNUM_MIN,  // AddressMinimum - Minimum Bus Number
+                    SYNQUACER_PCI_SEG1_BUSNUM_MIN,  // AddressMaximum - Maximum Bus Number
+                    0,                              // AddressTranslation - Set to 0
+                    1                               // RangeLength - Number of Busses
+                )
+
+                DWordMemory ( // 32-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length
+                )
+
+                QWordMemory ( // 64-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG1_MMIO64_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG1_MMIO64_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG1_MMIO64_SIZE      // Length
+                )
+
+                DWordIo ( // IO window
+                    ResourceProducer,
+                    MinFixed,
+                    MaxFixed,
+                    PosDecode,
+                    EntireRange,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG1_PORTIO_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG1_PORTIO_MAX,      // Max Base Address
+                    SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,  // Translate
+                    SYNQUACER_PCI_SEG1_PORTIO_SIZE,     // Length
+                    ,
+                    ,
+                    ,
+                    TypeTranslation
+                )
+            }) // Name(RBUF)
+
+            Return (RBUF)
+        } // Method(_CRS)
+
+        Device (RES0)
+        {
+            Name (_HID, "PNP0C02")
+            Name (_CRS, ResourceTemplate ()
+            {
+                Memory32Fixed (ReadWrite,
+                               SYNQUACER_PCI_SEG1_CONFIG_BASE,
+                               SYNQUACER_PCI_SEG1_CONFIG_SIZE)
+            })
+        }
+
+        //
+        // OS Control Handoff
+        //
+        Name(SUPP, Zero) // PCI _OSC Support Field value
+        Name(CTRL, Zero) // PCI _OSC Control Field value
+
+        /*
+      See [1] 6.2.10, [2] 4.5
+        */
+        Method(_OSC,4) {
+            // Check for proper UUID
+            If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+                // Create DWord-adressable fields from the Capabilities Buffer
+                CreateDWordField(Arg3,0,CDW1)
+                CreateDWordField(Arg3,4,CDW2)
+                CreateDWordField(Arg3,8,CDW3)
+
+                // Save Capabilities DWord2 & 3
+                Store(CDW2,SUPP)
+                Store(CDW3,CTRL)
+
+                // Only allow native hot plug control if OS supports:
+                // * ASPM
+                // * Clock PM
+                // * MSI/MSI-X
+                If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+                    And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+                }
+
+                // Always allow native PME, AER (no dependencies)
+
+                // Never allow SHPC (no SHPC controller in this system)
+                And(CTRL,0x1D,CTRL)
+
+                If(LNotEqual(Arg1,One)) {    // Unknown revision
+                    Or(CDW1,0x08,CDW1)
+                }
+
+                If(LNotEqual(CDW3,CTRL)) {    // Capabilities bits were masked
+                    Or(CDW1,0x10,CDW1)
+                }
+                // Update DWORD3 in the buffer
+                Store(CTRL,CDW3)
+                Return(Arg3)
+            } Else {
+                Or(CDW1,4,CDW1) // Unrecognized UUID
+                Return(Arg3)
+            }
+        } // End _OSC
+    } // PCI0
+  }
+}
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
new file mode 100644
index 000000000000..73fe4f5caa3e
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
@@ -0,0 +1,58 @@ 
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ACPITABLES_H__
+#define __ACPITABLES_H__
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_OEM_ID           'L','I','N','A','R','O'   // OEMID 6 bytes long
+#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('S','Y','N','Q','U','A','C','R') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM_REVISION     0x20170802
+#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('L','N','R','O')
+#define EFI_ACPI_CREATOR_REVISION 0x00000001
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define __ACPI_HEADER(Signature, Type, Revision) {                \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_OEM_ID },            /* UINT8   OemId[6] */        \
+    EFI_ACPI_OEM_TABLE_ID,          /* UINT64  OemTableId */      \
+    EFI_ACPI_OEM_REVISION,          /* UINT32  OemRevision */     \
+    EFI_ACPI_CREATOR_ID,            /* UINT32  CreatorId */       \
+    EFI_ACPI_CREATOR_REVISION       /* UINT32  CreatorRevision */ \
+  }
+
+#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
+  { \
+    EFI_ACPI_6_0_GICR, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), 0, RedisRegionAddr, RedisDiscLength \
+  }
+
+#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \
+  { EFI_ACPI_6_0_GIC_ITS, sizeof(EFI_ACPI_6_0_GIC_ITS_STRUCTURE), 0, Id, PhysAddress, 0 }
+
+#define EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhysicalAddress,                  \
+    ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags)                                 \
+  {                                                                                                     \
+    EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \
+    EFI_ACPI_RESERVED_WORD, RefreshFramePhysicalAddress, ControlFramePhysicalAddress,                   \
+    WatchdogTimerGSIV, WatchdogTimerFlags                                                               \
+  }
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..f390797b9d4f
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
@@ -0,0 +1,58 @@ 
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+#  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SynquacerAcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  AcpiTables.h
+  AcpiSsdtRootPci.asl
+  Dsdt.asl
+  Fadt.aslc
+  Gtdt.aslc
+  Iort.aslc
+  Madt.aslc
+  Mcfg.aslc
+  Spcr.aslc
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Socionext/Synquacer/Synquacer.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
new file mode 100644
index 000000000000..dc32a34ccfa2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
@@ -0,0 +1,168 @@ 
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "AcpiTables.h"
+
+#include <Platform/MemoryMap.h>
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
+  Scope(_SB) {
+    //
+    // A53x4 Processor declaration
+    //
+    Device(CP00) { // A53-0: Cluster 0, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 0)
+    }
+    Device(CP01) { // A53-0: Cluster 0, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 1)
+    }
+
+    Device(CP04) { // A53-0: Cluster 1, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 2)
+    }
+    Device(CP05) { // A53-0: Cluster 1, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 3)
+    }
+
+    Device(CP08) { // A53-0: Cluster 2, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 4)
+    }
+    Device(CP09) { // A53-0: Cluster 2, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 5)
+    }
+
+    Device(CP12) { // A53-0: Cluster 3, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 6)
+    }
+    Device(CP13) { // A53-0: Cluster 3, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 7)
+    }
+
+    Device(CP16) { // A53-0: Cluster 4, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 8)
+    }
+    Device(CP17) { // A53-0: Cluster 4, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 9)
+    }
+
+    Device(CP20) { // A53-0: Cluster 5, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 10)
+    }
+    Device(CP21) { // A53-0: Cluster 5, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 11)
+    }
+
+    Device(CP24) { // A53-0: Cluster 6, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 12)
+    }
+    Device(CP25) { // A53-0: Cluster 6, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 13)
+    }
+
+    Device(CP28) { // A53-0: Cluster 7, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 14)
+    }
+    Device(CP29) { // A53-0: Cluster 7, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 15)
+    }
+
+    Device(CP32) { // A53-0: Cluster 8, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 16)
+    }
+    Device(CP33) { // A53-0: Cluster 8, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 17)
+    }
+
+    Device(CP36) { // A53-0: Cluster 9, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 18)
+    }
+    Device(CP37) { // A53-0: Cluster 9, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 19)
+    }
+
+    Device(CP40) { // A53-0: Cluster 10, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 20)
+    }
+    Device(CP41) { // A53-0: Cluster 10, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 21)
+    }
+
+    Device(CP44) { // A53-0: Cluster 11, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 22)
+    }
+    Device(CP45) { // A53-0: Cluster 11, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 23)
+    }
+
+    // UART PL011
+    Device(COM0) {
+      Name(_HID, "ARMH0011")
+      Name(_CID, "PL011")
+      Name(_UID, Zero)
+      Name(_CRS, ResourceTemplate() {
+        Memory32Fixed(ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000)
+        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 }
+      })
+    }
+
+    Device(NET0) {
+      Name(_HID, "SCX0001")
+      Name(_UID, Zero)
+      Name(_CCA, Zero)
+      Name(_CRS, ResourceTemplate() {
+        Memory32Fixed(ReadWrite, SYNQUACER_NETSEC_BASE,
+                                 SYNQUACER_NETSEC_BASE_SZ)
+        Memory32Fixed(ReadWrite, SYNQUACER_EEPROM_BASE,
+                                 SYNQUACER_EEPROM_BASE_SZ)
+        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 208 }
+      })
+
+      Name (_DSD, Package ()  // _DSD: Device-Specific Data
+      {
+        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package (2) { "phy-mode", "rgmii" },
+          Package (2) { "phy-channel", 0x1 },
+          Package (2) { "max-speed", 1000 },
+          Package (2) { "max-frame-size", 9000 },
+          Package (2) { "socionext,phy-clock-frequency", 125000000 },
+        }
+      })
+    }
+  } // Scope(_SB)
+}
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
new file mode 100644
index 000000000000..26e4e0fc8964
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
@@ -0,0 +1,88 @@ 
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  __ACPI_HEADER (
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER,                                // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  EFI_ACPI_6_0_HW_REDUCED_ACPI | EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  EFI_ACPI_6_0_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
+  EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+  0                                                                         // UINT64     HypervisorVendorIdentity;
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
new file mode 100644
index 000000000000..f22c27f05454
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
@@ -0,0 +1,98 @@ 
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
+#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL       0
+
+#define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE                  TimerBase;
+  EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE            TimerFrame;
+  EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdog;
+} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  {
+    __ACPI_HEADER(
+      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES,
+      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+    ),
+    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
+    0,                                            // UINT32  Reserved
+    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
+    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
+    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
+    2,                                            // UINT32  PlatformTimerCount
+    sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+  },
+  {
+    EFI_ACPI_6_0_GTDT_GT_BLOCK,                                 // UINT8  Type
+    sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) +
+    sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE),        // UINT16 Length
+    EFI_ACPI_RESERVED_BYTE,                                     // UINT8  Reserved
+    0x2A810000,                                                 // UINT64 CntCtlBase
+    1,                                                          // UINT32 GTBlockTimerCount
+    sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE)               // UINT32 GTBlockTimerOffset
+  },
+  {
+    0,                                                          // UINT8  GTFrameNumber
+    {0, 0, 0},                                                  // UINT8  Reserved[3]
+    0x2A830000,                                                 // UINT64 CntBaseX
+    0xFFFFFFFFFFFFFFFF,                                         // UINT64 CntEL0BaseX
+    92,                                                         // UINT32 GTxPhysicalTimerGSIV
+    GTDT_TIMER_LEVEL_TRIGGERED | GTDT_TIMER_ACTIVE_HIGH,        // UINT32 GTxPhysicalTimerFlags
+    0,                                                          // UINT32 GTxVirtualTimerGSIV
+    0,                                                          // UINT32 GTxVirtualTimerFlags
+    EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY // UINT32 GTxCommonFlags
+  },
+  EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+    FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, 0),
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
new file mode 100644
index 000000000000..bbb425f1f808
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
@@ -0,0 +1,164 @@ 
+/** @file
+
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/IoRemappingTable.h>
+
+#include "AcpiTables.h"
+
+#define FIELD_OFFSET(type, name)            __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE        Node;
+  UINT32                                    Identifiers[1];
+} SYNQUACER_ITS_NODE;
+
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE       Node;
+  EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT        Context[2];
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE        RcIdMapping[1];
+} SYNQUACER_SMMU_NODE;
+
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_RC_NODE         Node;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE        RcIdMapping[1];
+} SYNQUACER_RC_NODE;
+
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_TABLE           Iort;
+  SYNQUACER_ITS_NODE                        ItsNode;
+  //SYNQUACER_SMMU_NODE                       Smmu;
+  SYNQUACER_RC_NODE                         RcNode[2];
+} SYNQUACER_IO_REMAPPING_STRUCTURE;
+
+#define __SYNQUACER_SMMU_NODE(Base, Size, Irq, NumIds)      \
+  {                                                         \
+    {                                                       \
+      EFI_ACPI_IORT_TYPE_SMMUv1v2,                          \
+      sizeof(SYNQUACER_SMMU_NODE),                          \
+      0x0,                                                  \
+      0x0,                                                  \
+      NumIds,                                               \
+      FIELD_OFFSET(SYNQUACER_SMMU_NODE, RcIdMapping),       \
+    },                                                      \
+    Base,                                                   \
+    Size,                                                   \
+    EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500,                    \
+    0,                                                      \
+    FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE,       \
+                 SMMU_NSgIrpt),                             \
+    0x2,                                                    \
+    sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE),            \
+    0x0,                                                    \
+    0x0,                                                    \
+    Irq,                                                    \
+    EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL,                  \
+    0x0,                                                    \
+    0x0,                                                    \
+  }, {                                                      \
+    {                                                       \
+      Irq,                                                  \
+      EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL,                \
+    },                                                      \
+    {                                                       \
+      Irq,                                                  \
+      EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL,                \
+    },                                                      \
+  }
+
+#define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags)    \
+  {                                                         \
+    In,                                                     \
+    Num,                                                    \
+    Out,                                                    \
+    FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, Ref),    \
+    Flags                                                   \
+  }
+
+STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
+  {
+    __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
+                  SYNQUACER_IO_REMAPPING_STRUCTURE,
+                  EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
+    3,                                              // NumNodes
+    sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE),        // NodeOffset
+    0                                               // Reserved
+  }, {
+    // ItsNode
+    {
+      {
+        EFI_ACPI_IORT_TYPE_ITS_GROUP,                       // Type
+        sizeof(SYNQUACER_ITS_NODE),                         // Length
+        0x0,                                                // Revision
+        0x0,                                                // Reserved
+        0x0,                                                // NumIdMappings
+        0x0,                                                // IdReference
+      },
+      1,
+    }, {
+      0x0
+    },
+  }, {
+//     __SYNQUACER_SMMU_NODE(0x582C0000, 0x10000, 234, 1),
+//     { __SYNQUACER_ID_MAPPING(0x200, 0x0, 0x0, ItsNode, 0x0), }
+//  }, {
+    // PciRcNode
+    {
+      {
+        {
+          EFI_ACPI_IORT_TYPE_ROOT_COMPLEX,                    // Type
+          sizeof(SYNQUACER_RC_NODE),                          // Length
+          0x0,                                                // Revision
+          0x0,                                                // Reserved
+          0x1,                                                // NumIdMappings
+          FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping),       // IdReference
+        },
+        EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,                    // CacheCoherent
+        0x0,                                                  // AllocationHints
+        0x0,                                                  // Reserved
+        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
+        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS,                  // MemoryAccessFlags
+        EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,           // AtsAttribute
+        0x0,                                                  // PciSegmentNumber
+      }, {
+        __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
+      },
+    }, {
+      // PciRcNode
+      {
+        {
+          EFI_ACPI_IORT_TYPE_ROOT_COMPLEX,                    // Type
+          sizeof(SYNQUACER_RC_NODE),                          // Length
+          0x0,                                                // Revision
+          0x0,                                                // Reserved
+          0x1,                                                // NumIdMappings
+          FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping),       // IdReference
+        },
+        EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,                    // CacheCoherent
+        0x0,                                                  // AllocationHints
+        0x0,                                                  // Reserved
+        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
+        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS,                  // MemoryAccessFlags
+        EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,           // AtsAttribute
+        0x1,                                                  // PciSegmentNumber
+      }, {
+        __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
+      }
+    }
+  }
+};
+
+#pragma pack()
+
+VOID* CONST ReferenceAcpiTable = &Iort;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
new file mode 100644
index 000000000000..a8c27dcf8923
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
@@ -0,0 +1,152 @@ 
+/** @file
+*  Multiple APIC Description Table (MADT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_6_0_GIC_STRUCTURE                            GicInterfaces[FixedPcdGet32 (PcdClusterCount) * FixedPcdGet32 (PcdCoreCount)];
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_0_GICR_STRUCTURE                           GicRedistributor;
+  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                        GicIts;
+} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  {
+    __ACPI_HEADER (
+      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+    ),
+    //
+    // MADT specific fields
+    //
+    0, // LocalApicAddress
+    0, // Flags
+  },
+  {
+    // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, GicBase, GicVBase,
+    //                                          GicHBase, GsivId, GicRBase)
+    // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+    //       ACPI v6.0).
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
+        0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-1
+        0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-2
+        0, 2, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-3
+        0, 3, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-4
+        0, 4, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-5
+        0, 5, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-6
+        0, 6, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-7
+        0, 7, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-8
+        0, 8, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-9
+        0, 9, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-10
+        0, 10, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-11
+        0, 11, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-12
+        0, 12, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-13
+        0, 13, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-14
+        0, 14, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-15
+        0, 15, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-16
+        0, 16, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-17
+        0, 17, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-18
+        0, 18, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-19
+        0, 19, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-20
+        0, 20, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-21
+        0, 21, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-22
+        0, 22, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-23
+        0, 23, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+  },
+  // GIC Distributor Entry
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3),
+  // GIC Redistributor
+  EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), 0x300000),
+  // GIC ITS
+  EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000)
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
new file mode 100644
index 000000000000..00df5f181de3
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
@@ -0,0 +1,63 @@ 
+/** @file
+
+  ACPI Memory mapped configuration space base address Description Table (MCFG).
+  Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+  downloadable at http://www.pcisig.com/home
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+  Copyright (c) 2017, Linaro Limited. All rights reserved.
+
+  This program and the accompanying materials are licensed and
+  made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the
+  license may be found at http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <Platform/Pcie.h>
+
+#include "AcpiTables.h"
+
+#pragma pack(push, 1)
+
+typedef struct {
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
+  {
+    __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+    EFI_ACPI_RESERVED_QWORD
+  },
+  {
+    {
+      SYNQUACER_PCI_SEG0_CONFIG_BASE | 0x8000,
+      0,
+      SYNQUACER_PCI_SEG0_BUSNUM_MIN,
+      SYNQUACER_PCI_SEG0_BUSNUM_MIN,
+      EFI_ACPI_RESERVED_DWORD
+    }, {
+      SYNQUACER_PCI_SEG1_CONFIG_BASE | 0x8000,
+      1,
+      SYNQUACER_PCI_SEG1_BUSNUM_MIN,
+      SYNQUACER_PCI_SEG1_BUSNUM_MIN,
+      EFI_ACPI_RESERVED_DWORD
+    }
+  }
+};
+
+#pragma pack(pop)
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
new file mode 100644
index 000000000000..f51475e5c6a2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
@@ -0,0 +1,127 @@ 
+/** @file
+
+  Serial Port Console Redirection Table
+  (c) 2000 - 2014 Microsoft Corporation. All rights reserved.
+  http://go.microsoft.com/fwlink/?linkid=403368
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#include "AcpiTables.h"
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+  //
+  // Header
+  //
+  __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+                 EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+                 2), /* New MS definition for PL011 support */
+  //
+  // InterfaceType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+  //
+  // Reserved[3]
+  //
+  { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+  //
+  // BaseAddress
+  //
+  {
+    EFI_ACPI_5_1_SYSTEM_MEMORY,
+    32,
+    0,
+    EFI_ACPI_5_1_DWORD,
+    FixedPcdGet32 (PcdSerialRegisterBase)
+  },
+  //
+  // InterruptType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+  //
+  // Irq
+  //
+  0,
+  //
+  // GlobalSystemInterrupt
+  //
+  95,
+  //
+  // BaudRate
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+  //
+  // Parity
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+  //
+  // StopBits
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+  //
+  // FlowControl
+  //
+  0,
+  //
+  // TerminalType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+  //
+  // Language
+  //
+  EFI_ACPI_RESERVED_BYTE,
+  //
+  // PciDeviceId
+  //
+  0xFFFF,
+  //
+  // PciVendorId
+  //
+  0xFFFF,
+  //
+  // PciBusNumber
+  //
+  0x00,
+  //
+  // PciDeviceNumber
+  //
+  0x00,
+  //
+  // PciFunctionNumber
+  //
+  0x00,
+  //
+  // PciFlags
+  //
+  0,
+  //
+  // PciSegment
+  //
+  0,
+  //
+  // Reserved2
+  //
+  EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;