From patchwork Mon Sep 11 13:52:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112191 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825760pji; Mon, 11 Sep 2017 06:51:51 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7+5eet8Nmd191ItMIu5w+DkC20oHdNpRzaMg42JYbzfKJsH4OeMcVcswmd57ASubJgWYpf X-Received: by 10.99.97.148 with SMTP id v142mr12222283pgb.413.1505137911167; Mon, 11 Sep 2017 06:51:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137911; cv=none; d=google.com; s=arc-20160816; b=SsvNufbIF8+uLVdXB3XSDxtbxfN3RUcdW8g92M9oyzayQWD8SaWi4m/LgobvPNhBu6 SPmyJCiyCkSwRpSnYKrir3o6XS8i6bfYHqfHuIOP9rIONN/cV4FWo1trYOc18HEF2fgl oUiE/JmkmLR1F597mPpPrr+EcS0oUVA0Y6mkUrZsiCB5uk8N7CQkAFon4D61pUzVgC1u n67PhjaPC8mZV3f07+MdHJn6FTjGBwMMgwY6UIzLJ4KG+hvPcuBpcfuMSa6HDFJECxw5 2LyZ1AGAD8ljhPEr1CvNq5+PSrzeL4MOfzQmFZDoDhxkQzM5ypCbE6zbuIo1o20uGlhV oPUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Cw1uYhjDSVmI8ptdsucthUFSvhXnPYZcwKfVp+ghky0=; b=ERkVyamscu9prqpUU0SIOp0aHqiNyNqPJ4rwipNKoQw88FGSUvcpvlQPX//l+uf+8I iPrz9Tfi5Z9xr6q6Rmb/JnDW3iMBjEsyR08KZUVAg59hOyqQSw0bldRqmOGuHIeR+uVV xNgihg+UANA88ie6zLX1piGB7GpbLP+O0EjN3+icY9+ZyBk6wbxyNloqIW+X/O5cMUZn 19VVq/Nw9vSdDWuAQjAW2cty/U2m0bODRzBSwuFqE7SptV6Gt/TKdpvPTGyC/IypKSFU JEMXROLg5iZUW7Kn22X7XkVRYpklTsWdpUdhpupGqfJWr2TCpJVLgVqeSvCXK/S8MrC2 sloA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id i35si6807301plg.722.2017.09.11.06.51.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7p-0007lo-Gn; Mon, 11 Sep 2017 14:51:45 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 1/7] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 Date: Mon, 11 Sep 2017 14:52:04 +0100 Message-Id: <1505137930-13255-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Use a symbolic constant M_REG_NUM_BANKS for the array size for registers which are banked by M profile security state, rather than hardcoding lots of 2s. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- Philippe suggested this in review on the last round of patches but I forgot about it :-( --- target/arm/cpu.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26..5a1f957 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -81,8 +81,11 @@ * accessed via env->registerfield[env->v7m.secure] (whether the security * extension is implemented or not). */ -#define M_REG_NS 0 -#define M_REG_S 1 +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 @@ -433,19 +436,19 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t other_ss_msp; uint32_t other_ss_psp; - uint32_t vecbase[2]; - uint32_t basepri[2]; - uint32_t control[2]; - uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr[2]; /* Configurable Fault Status */ + uint32_t vecbase[M_REG_NUM_BANKS]; + uint32_t basepri[M_REG_NUM_BANKS]; + uint32_t control[M_REG_NUM_BANKS]; + uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ + uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar[2]; /* MemManage Fault Address */ + uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl[2]; /* MPU_CTRL */ + unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ int exception; - uint32_t primask[2]; - uint32_t faultmask[2]; + uint32_t primask[M_REG_NUM_BANKS]; + uint32_t faultmask[M_REG_NUM_BANKS]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; @@ -546,7 +549,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr[2]; + uint32_t rnr[M_REG_NUM_BANKS]; } pmsav7; /* PMSAv8 MPU */ @@ -556,10 +559,10 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar[2]; - uint32_t *rlar[2]; - uint32_t mair0[2]; - uint32_t mair1[2]; + uint32_t *rbar[M_REG_NUM_BANKS]; + uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t mair0[M_REG_NUM_BANKS]; + uint32_t mair1[M_REG_NUM_BANKS]; } pmsav8; void *nvic;