From patchwork Mon Sep 11 13:52:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112192 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825800pji; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4QtxF/LkZdoF2Q1nOGhzVIeC0NRtIUvNvz4ZHSrIXoepP4dwV4tRdkczRCyKoKwVPy7Wsr X-Received: by 10.98.196.73 with SMTP id y70mr11943784pff.334.1505137912749; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137912; cv=none; d=google.com; s=arc-20160816; b=0pM1OzDmZi6t0DzK9zKAMzvgO+qkak3k0QmqrRkLzI7+VI4hYWkGkyCusSejFW0wY1 y18eBeYAJCZyAKEbx+rh7Ov+6bBsqhKWsDA/wuxxD1ynu38phFOMbte6GhSo+hTXPjGc JpCBqZkh4XOU3MR2aBKmXlCWS0GllLk84Q9V5Ck55o2FEN7D7IwvsT7Wenxj3UtuHHKG Efitej879p7Wmx9U6tC1L6G8mKWD1TZ728YMx1kttaIwd+w/5J7i3PPWKsj/fng3k1T8 JO9whTjZA+fKaOwvaVBPutbnmvefHtL5sWIMkCqfeRiNCS2RGCEPbzKDyoTKq5WDaX2v dP6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=ak6eDkVOr9wRUe7yevzq9xJxkTkFAKk1+BvJtSbvFWQ=; b=kbS3PnN8c8rHau5ld+WC1vAV0tvbVXauZckfSWpx/ZxkUj0ADadUo5EBZwdmzjk2Da 7CxpFmbHNbrSnOFgPyKFegQVg9dvxvmTuoAoMbNCjfj8sj9wUSCFSXER8gCS9b5xvHAN 7d718ziUlfWUqbaXjnHC2hov/XCXt8VwdXsP3LEnkL8w+xwZQ7caILMYrTHuuVQf4REB +dKaY9MMIHKYsbNFU1ptyPi90q+CLGhLZoIIg1/VNC9psImfA9RFF4gicaETpzBbjdNQ 9d/T9Egmy9+PzBSG045WNGYB7bWozHPAR1PQgIvS3q8tKCOuzMb9e/fSWilz5vKyHFpr ROPw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id d2si5963935pge.795.2017.09.11.06.51.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7q-0007mE-Rl; Mon, 11 Sep 2017 14:51:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 3/7] target/arm: Get PRECISERR and IBUSERR the right way round Date: Mon, 11 Sep 2017 14:52:06 +0100 Message-Id: <1505137930-13255-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> For a bus fault, the M profile BFSR bit PRECISERR means a bus fault on a data access, and IBUSERR means a bus fault on an instruction access. We had these the wrong way around; fix this. Signed-off-by: Peter Maydell --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 668e367..1741e0d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6430,15 +6430,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case 0x8: /* External Abort */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK; - qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); break; case EXCP_DATA_ABORT: env->v7m.cfsr[M_REG_NS] |= - (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); env->v7m.bfar = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, - "...with CFSR.IBUSERR and BFAR 0x%x\n", + "...with CFSR.PRECISERR and BFAR 0x%x\n", env->v7m.bfar); break; }