From patchwork Mon Sep 11 13:52:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112194 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825804pji; Mon, 11 Sep 2017 06:51:53 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4rQxFuEpw/SoBiG3tT30XazHOwDXxwYbxu0B/UXnKqvHOKYcAnIXHHkh7pHeaJ4aaBSodD X-Received: by 10.98.100.206 with SMTP id y197mr12150320pfb.53.1505137912954; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137912; cv=none; d=google.com; s=arc-20160816; b=JOMCUjMJy1bNKMR2Q5pcyKElI4V4wMOKi1iVmhY0nK05bAkDbzRWTovhJFd5nItxkd euAZN4D0dabbw6cw/UPXHily5zI1AVrrmHND65orbM63FPWmdu8p7NGCw+EQdTuRlehP SBjDU5V/4XIv7WjEcrtwL6QbqWc9uQZMycfX/TUXGk1p+tjJYxGMJq7AUddLp9rNZ8p7 sRCnj89s6nxeOQTBtSaZctqRFXS1uWiOcWgxLtDc2MUZbi810LyDLNflmY6oWoOwZyB4 yDzyz65wthOmFuP/ZOchRBoFNyriQVz6/bt+xEF3C6wMK5rrhtU2Q1mDAQt2lxguUGnz SL8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=BWsjrYSavSxCnT1vxbk0oAog74deWZZ/WZ4O5Nys86A=; b=O62yQA5wByb3U1TQq+4WwIFtyxQKug6UQ75nxHZtP/n+uTltVmjjSJMOtazEQfbzO3 DYClHd9GPane+bZMbA0loTpePIwSRKcdl1PDa/SlCaR3XFY25++XEoSPFhvK7GoD6PAy GfL3T/c2y7hEn/OMnad0tFQnhnpnuZ6my8saNSoofsVsD7z0qFIlGgrb3Oik1gyBVQgh iNNGqa25h/H12Sg6rU+JvHaA0KvyaZtXyaTfxFPQ58dO9ePJuZoF9IWnR2fkb4SIdAyX zXjvFtmVbW2Zdhcv1CrBXmAwt91guVyzVBeV/8kDykfHNSbH2E0NF5tlX2ifibtL77Uo vypQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j188si3244968pfb.412.2017.09.11.06.51.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7s-0007mr-VD; Mon, 11 Sep 2017 14:51:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 6/7] target/arm: Add and use defines for EXCRET constants Date: Mon, 11 Sep 2017 14:52:09 +0100 Message-Id: <1505137930-13255-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> The exception-return magic values get some new bits in v8M, which makes some bit definitions for them worthwhile. We don't use the bit definitions for the switch on the low bits which checks the return type for v7M, because this is defined in the v7M ARM ARM as a set of valid values rather than via per-bit checks. Signed-off-by: Peter Maydell --- target/arm/internals.h | 10 ++++++++++ target/arm/helper.c | 14 +++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) -- 2.7.4 Reviewed-by: Alistair Francis diff --git a/target/arm/internals.h b/target/arm/internals.h index a315354..18be370 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -61,6 +61,16 @@ FIELD(V7M_CONTROL, NPRIV, 0, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, FPCA, 2, 1) +/* Bit definitions for v7M exception return payload */ +FIELD(V7M_EXCRET, ES, 0, 1) +FIELD(V7M_EXCRET, RES0, 1, 1) +FIELD(V7M_EXCRET, SPSEL, 2, 1) +FIELD(V7M_EXCRET, MODE, 3, 1) +FIELD(V7M_EXCRET, FTYPE, 4, 1) +FIELD(V7M_EXCRET, DCRS, 5, 1) +FIELD(V7M_EXCRET, S, 6, 1) +FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/helper.c b/target/arm/helper.c index fdd5cc6..a502e4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6242,7 +6242,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) " previous exception %d\n", type, env->v7m.exception); - if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { + if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); } @@ -6255,7 +6255,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es = type & 1; + int es = type & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { env->v7m.faultmask[es] = 0; } @@ -6491,12 +6491,16 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } - lr = 0xfffffff1; + lr = R_V7M_EXCRET_RES1_MASK | + R_V7M_EXCRET_S_MASK | + R_V7M_EXCRET_DCRS_MASK | + R_V7M_EXCRET_FTYPE_MASK | + R_V7M_EXCRET_ES_MASK; if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { - lr |= 4; + lr |= R_V7M_EXCRET_SPSEL_MASK; } if (!arm_v7m_is_handler_mode(env)) { - lr |= 8; + lr |= R_V7M_EXCRET_MODE_MASK; } v7m_push_stack(cpu);