[v2] ARM: dts: exynos: Add power button for Odroid XU3/4

Message ID 1505217474-14725-1-git-send-email-m.szyprowski@samsung.com
State New
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  • [v2] ARM: dts: exynos: Add power button for Odroid XU3/4
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Commit Message

Marek Szyprowski Sept. 12, 2017, 11:57 a.m.
From: Brian Kim <brian.kim@hardkernel.com>


The power button (SW2) on Odroid XU3/4 is connected to the PWRON pin
of the S2MPS11 PMIC.

The S2MPS11 datasheet says that ONOB pin operates as 'PWRON key active
low signal'. In fact, S2MPS11 PMIC acts as a 16ms debouce filter and
signal inverter, thus effectively repeating PWRON (active high) to ONOB
pin (active low).

ONOB PMIC pin is then connected to XEINT3 SoC pin, so we get the state
of the power button on the gpx0-3 GPIO.

This patch adds device-tree bindings for the power button of Odroid
XU3/4 boards.

Signed-off-by: Brian Kim <brian.kim@hardkernel.com>

[mszyprow: extended commit message, added comments and fixed minor
 issues in the dts]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
Changelog:

v2: fixed minor issues pointed by Krzysztof Kozlowski:
- added comments to dts
- extended commit message
- removed useless interrupts property
- used proper macros for gpios
- removed gpio prefix

v1: initial submission
https://patchwork.kernel.org/patch/9605023/

---
 arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

-- 
1.9.1

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Comments

Anand Moon Sept. 18, 2017, 4:07 a.m. | #1
Hi Marek,

On 12 September 2017 at 17:27, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> From: Brian Kim <brian.kim@hardkernel.com>

>

> The power button (SW2) on Odroid XU3/4 is connected to the PWRON pin

> of the S2MPS11 PMIC.

>

> The S2MPS11 datasheet says that ONOB pin operates as 'PWRON key active

> low signal'. In fact, S2MPS11 PMIC acts as a 16ms debouce filter and

> signal inverter, thus effectively repeating PWRON (active high) to ONOB

> pin (active low).

>

> ONOB PMIC pin is then connected to XEINT3 SoC pin, so we get the state

> of the power button on the gpx0-3 GPIO.

>

> This patch adds device-tree bindings for the power button of Odroid

> XU3/4 boards.

>

> Signed-off-by: Brian Kim <brian.kim@hardkernel.com>

> [mszyprow: extended commit message, added comments and fixed minor

>  issues in the dts]

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---

> Changelog:

>

> v2: fixed minor issues pointed by Krzysztof Kozlowski:

> - added comments to dts

> - extended commit message

> - removed useless interrupts property

> - used proper macros for gpios

> - removed gpio prefix

>

> v1: initial submission

> https://patchwork.kernel.org/patch/9605023/

>


Please add my

Reviewed-by: Anand Moon <linux.amoon@gmail.com>

Tested-by: Anand Moon <linux.amoon@gmail.com>


Best Regards
-Anand Moon
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Krzysztof Kozlowski Sept. 18, 2017, 6:37 p.m. | #2
On Tue, Sep 12, 2017 at 01:57:54PM +0200, Marek Szyprowski wrote:
> From: Brian Kim <brian.kim@hardkernel.com>

> 

> The power button (SW2) on Odroid XU3/4 is connected to the PWRON pin

> of the S2MPS11 PMIC.

> 

> The S2MPS11 datasheet says that ONOB pin operates as 'PWRON key active

> low signal'. In fact, S2MPS11 PMIC acts as a 16ms debouce filter and

> signal inverter, thus effectively repeating PWRON (active high) to ONOB

> pin (active low).

> 

> ONOB PMIC pin is then connected to XEINT3 SoC pin, so we get the state

> of the power button on the gpx0-3 GPIO.

> 

> This patch adds device-tree bindings for the power button of Odroid

> XU3/4 boards.

> 

> Signed-off-by: Brian Kim <brian.kim@hardkernel.com>

> [mszyprow: extended commit message, added comments and fixed minor

>  issues in the dts]

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---

> Changelog:

> 

> v2: fixed minor issues pointed by Krzysztof Kozlowski:

> - added comments to dts

> - extended commit message

> - removed useless interrupts property

> - used proper macros for gpios

> - removed gpio prefix

> 

> v1: initial submission

> https://patchwork.kernel.org/patch/9605023/

> 

> ---

>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 29 ++++++++++++++++++++++

>  1 file changed, 29 insertions(+)

>


Thanks, Marek (and Bartlomiej from other thread), for working on these
patches. Nice job!

Applied.

Best regards,
Krzysztof

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Anand Moon Sept. 24, 2017, 7:52 p.m. | #3
Hi Marek/Krzysztof,

On 12 September 2017 at 17:27, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> From: Brian Kim <brian.kim@hardkernel.com>

>

> The power button (SW2) on Odroid XU3/4 is connected to the PWRON pin

> of the S2MPS11 PMIC.

>

> The S2MPS11 datasheet says that ONOB pin operates as 'PWRON key active

> low signal'. In fact, S2MPS11 PMIC acts as a 16ms debouce filter and

> signal inverter, thus effectively repeating PWRON (active high) to ONOB

> pin (active low).

>

> ONOB PMIC pin is then connected to XEINT3 SoC pin, so we get the state

> of the power button on the gpx0-3 GPIO.

>

> This patch adds device-tree bindings for the power button of Odroid

> XU3/4 boards.

>

> Signed-off-by: Brian Kim <brian.kim@hardkernel.com>

> [mszyprow: extended commit message, added comments and fixed minor

>  issues in the dts]

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---

> Changelog:

>

> v2: fixed minor issues pointed by Krzysztof Kozlowski:

> - added comments to dts

> - extended commit message

> - removed useless interrupts property

> - used proper macros for gpios

> - removed gpio prefix

>

> v1: initial submission

> https://patchwork.kernel.org/patch/9605023/


[snip]

Is their another way to reset the S2MPS11 PMIC during software reboot.
what I mean is the clear all the previously programmed output voltage
in the internal registers.
the reason I am asking this all the peripherals attached to the board
do not reset to initial states.
for example scdard/emmc and usb ports do not reset when we performer reboot.

What would be the correct way to so reset of S2MPS11 PMIC during
software reboot.

Best Regards
-Anand
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Patch

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index a183b56283f8..29a718ae621a 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -13,6 +13,7 @@ 
 */
 
 #include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/sound/samsung-i2s.h>
@@ -41,6 +42,27 @@ 
 		};
 	};
 
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+
+		power_key {
+			/*
+			 * The power button (SW2) is connected to the PWRON
+			 * pin (active high) of the S2MPS11 PMIC, which acts
+			 * as a 16ms debouce filter and signal inverter with
+			 * output on ONOB pin (active low). ONOB PMIC pin is
+			 * then connected to XEINT3 SoC pin.
+			 */
+			gpios = <&gpx0 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			label = "power key";
+			debounce-interval = <0>;
+			wakeup-source;
+		};
+	};
+
 	emmc_pwrseq: pwrseq {
 		pinctrl-0 = <&emmc_nrst_pin>;
 		pinctrl-names = "default";
@@ -561,6 +583,13 @@ 
 };
 
 &pinctrl_0 {
+	power_key: power-key {
+		samsung,pins = "gpx0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
 	hdmi_hpd_irq: hdmi-hpd-irq {
 		samsung,pins = "gpx3-7";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;