From patchwork Tue Sep 12 18:13:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112349 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5548941qgf; Tue, 12 Sep 2017 11:13:42 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAqjexoB2FMCX/oUGt+FASgpmaRbWTTTbSL/kjXfjqLby0nm21I5FwWjclEh3QIuXS9GO/Y X-Received: by 10.46.23.25 with SMTP id l25mr2746460lje.178.1505240022818; Tue, 12 Sep 2017 11:13:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505240022; cv=none; d=google.com; s=arc-20160816; b=gUAo5ecFjDK66n+rOVJhcePie1NBRx83Hu4vaXivknOgJzt7+TC093/4CEoLyYv06R 9WVfcMgsTvRUE1LT8JCN8zKTjfO8lsFiqRdf5DuPCDG1vs2W3DNBOvNR5Js5ghWGxa1m vSg08Pyg26Fa2DFwUVhqciKR4EFenyryqIAFCDHm/9TRyPNHXbfbuErDO+MldmzdnUFh Fc/BbAEI8JjCPy9yysZIP0LyGYdCUWWVm0E+/h9eSiR+zLoNpNPoBvrOOq3Htatcpp3Q s+quAX5/4aqHNF9UQfo5h1ke1KTR1PqstzdR63ASHCUZbrENLzyguLl45w36PMbD2XJE P9Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=0RdA84HwaRVq1HY6y6uO6ARE7wTHWisiKDdMt0RMmtc=; b=uqCLjKdWKz6/CBDAdtaBtxIDBkP8fkYvw7/Af3jWpIFJf4vnSDJtkGuQkys8xia2I8 d8bVNgmkb3Os9qksjydfZHj5POmGf3BVo2NPK21gvZpTGA6xXlxSPs9y5wWPwUnoJb9f UAaTA3zgkb5Uwb3oucPoJTqmNxPH78yZyD6964JPF5Ky73yI4lUnAgofG0LeZs6krJpg 2txGkfHgbIh7qd9yu2AuSfWlPRxQ9O7FriNeIBQ35vKdC2DehH6maL8BntpaybbSGj9H rHmw0YSnpqRl8MN4ZIdKVxBami4ZnsLsM4WfIqP763+AO6erotHIjOl/VmlLo3XslYep 5mhw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id m141si4479533lfg.617.2017.09.12.11.13.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 11:13:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drpgr-00013V-Hy; Tue, 12 Sep 2017 19:13:41 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 03/19] nvic: Add cached vectpending_is_s_banked state Date: Tue, 12 Sep 2017 19:13:50 +0100 Message-Id: <1505240046-11454-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> References: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> With banked exceptions, just the exception number in s->vectpending is no longer sufficient to uniquely identify the pending exception. Add a vectpending_is_s_banked bool which is true if the exception is using the sec_vectors[] array. Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 11 +++++++++-- hw/intc/armv7m_nvic.c | 1 + 2 files changed, 10 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 317601e..87c78b3 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -57,10 +57,17 @@ typedef struct NVICState { VecInfo sec_vectors[NVIC_INTERNAL_VECTORS]; uint32_t prigroup; - /* vectpending and exception_prio are both cached state that can - * be recalculated from the vectors[] array and the prigroup field. + /* The following fields are all cached state that can be recalculated + * from the vectors[] and sec_vectors[] arrays and the prigroup field: + * - vectpending + * - vectpending_is_secure + * - exception_prio */ unsigned int vectpending; /* highest prio pending enabled exception */ + /* true if vectpending is a banked secure exception, ie it is in + * sec_vectors[] rather than vectors[] + */ + bool vectpending_is_s_banked; int exception_prio; /* group prio of the highest prio active exception */ MemoryRegion sysregmem; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 694b9e0..417a456 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1250,6 +1250,7 @@ static void armv7m_nvic_reset(DeviceState *dev) s->exception_prio = NVIC_NOEXC_PRIO; s->vectpending = 0; + s->vectpending_is_s_banked = false; } static void nvic_systick_trigger(void *opaque, int n, int level)