From patchwork Tue Sep 12 18:13:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112354 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5548995qgf; Tue, 12 Sep 2017 11:13:45 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4dntSFgSN2v7cWKOOnWz7OL3GJdWHm5lQCDylJsCACOT76XmwlQWSZTpUmZyabuqQhDXqL X-Received: by 10.99.176.14 with SMTP id h14mr15820430pgf.358.1505240025325; Tue, 12 Sep 2017 11:13:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505240025; cv=none; d=google.com; s=arc-20160816; b=jxxvdcv33o6AP5iJvWoHbqqLsyexrmnZLgIUc/ulesNzA3JYjLSvbeWgEnpGbbdHYz ipb1Y93DMKL78KTTFc9bF45osmTuv/TXggGnsRl0WkawhcBdbQoZAt5pMcgVKx11FNeJ E2j7+VmCwoi/1p3mCsU5OpH7EY8z89yVY+WMVWfdR1jInjlju2h/p8nw7O3Glcy03k2A qOI0ic0hZXbOmPwn6qRJTvBfdquoekiMUZDBhKaELurIA0HXakTDJsQsFWNxBZYHfcZQ bBG9PNvSF1o+XMD0JC324hDFB6++QPZhqqH66ZL0TUxNkuJ6uk0opp7ao1Oy3VU5wgf2 RDJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=kQsJmKLqlo0zU/tVNsuqSlH51deGiBgTiRR53dwMu9M=; b=S14WQypYqjcTb7ruA1YjMTi4vVJ/Greg1tjUUHDqK6JRewqzCfFtytLLH766T3ELLJ w4v/eHy92nh9wA53ds+HA3C3bHpob2suCb5v0wkm07f8BwOO0CrLBAGxKcrxW3+0QYvD veHZ0jZP2nc3kto3aFJMoo0LzH8X/cCVOkoy/PjuWc5ZUUE1TpA0RQI1Od47zxvVOY31 tSTk6OAL1qrlQmUkeBeDgOBurpw6C9UzZQccQZsRqIZwhjWn3SJwXY6/WC5ersCnxoAG NEtJaZuo5Q7Ty0G/O11YnZ1GXt7oDpd76M7/6hlYYUv+UtG3ZnmbAfM9ykuCfhMy5kck LzBA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id g6si9111044pll.236.2017.09.12.11.13.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 11:13:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drpgq-00012z-9z; Tue, 12 Sep 2017 19:13:40 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 01/19] target/arm: Implement MSR/MRS access to NS banked registers Date: Tue, 12 Sep 2017 19:13:48 +0100 Message-Id: <1505240046-11454-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> References: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> In v8M the MSR and MRS instructions have extra register value encodings to allow secure code to access the non-secure banked version of various special registers. (We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because we don't currently implement the stack limit registers at all.) Signed-off-by: Peter Maydell --- target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 4f41841..f4f2a87 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8892,12 +8892,68 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) break; case 20: /* CONTROL */ return env->v7m.control[env->v7m.secure]; + case 0x94: /* CONTROL_NS */ + /* We have to handle this here because unprivileged Secure code + * can read the NS CONTROL register. + */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.control[M_REG_NS]; } if (el == 0) { return 0; /* unprivileged reads others as zero */ } + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + switch (reg) { + case 0x88: /* MSP_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.other_ss_msp; + case 0x89: /* PSP_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.other_ss_psp; + case 0x90: /* PRIMASK_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.primask[M_REG_NS]; + case 0x91: /* BASEPRI_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.basepri[M_REG_NS]; + case 0x93: /* FAULTMASK_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.faultmask[M_REG_NS]; + case 0x98: /* SP_NS */ + { + /* This gives the non-secure SP selected based on whether we're + * currently in handler mode or not, using the NS CONTROL.SPSEL. + */ + bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; + + if (!env->v7m.secure) { + return 0; + } + if (!arm_v7m_is_handler_mode(env) && spsel) { + return env->v7m.other_ss_psp; + } else { + return env->v7m.other_ss_msp; + } + } + default: + break; + } + } + switch (reg) { case 8: /* MSP */ return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ? @@ -8936,6 +8992,60 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) return; } + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + switch (reg) { + case 0x88: /* MSP_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.other_ss_msp = val; + return; + case 0x89: /* PSP_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.other_ss_psp = val; + return; + case 0x90: /* PRIMASK_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.primask[M_REG_NS] = val & 1; + return; + case 0x91: /* BASEPRI_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.basepri[M_REG_NS] = val & 0xff; + return; + case 0x93: /* FAULTMASK_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.faultmask[M_REG_NS] = val & 1; + return; + case 0x98: /* SP_NS */ + { + /* This gives the non-secure SP selected based on whether we're + * currently in handler mode or not, using the NS CONTROL.SPSEL. + */ + bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; + + if (!env->v7m.secure) { + return; + } + if (!arm_v7m_is_handler_mode(env) && spsel) { + env->v7m.other_ss_psp = val; + } else { + env->v7m.other_ss_msp = val; + } + return; + } + default: + break; + } + } + switch (reg) { case 0 ... 7: /* xPSR sub-fields */ /* only APSR is actually writable */