From patchwork Tue Sep 12 18:13:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112359 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5549045qgf; Tue, 12 Sep 2017 11:13:48 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBDbq44d5aXC34XScJJG4FBSdUh7AO4/rrp3+ZipnR9f5EEz1p2ADaXSqsAPG7fME4bFgIe X-Received: by 10.28.232.138 with SMTP id f10mr335900wmi.130.1505240028370; Tue, 12 Sep 2017 11:13:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505240028; cv=none; d=google.com; s=arc-20160816; b=XBRyh8KuuV6dchN5ub4jGPjO6DdOnA8dH4Z38zzcmxao6nMUMUiZki0OZSZX2pdJIN zoyzZmRyUbUNe6SofqfVG3DUb8W3SE++Gome5+BueT8wYSj2tVGtSj4b/KTw9eHDsjDG ++81+xWVafyJlG02CzP8p0zJP6t43IwRVf5u6rIB6ECm1V1VILCr/1bdhWVhihMWbTdG NGo/aRJESgX9c3Hpfx/xlMdEcjns/seo3+Vh1cipexSI5bUnVFrPzrxezMAGmrQ6CCyK W7qXkqOKOl7jynQ0KgxkM2M8kek4SVL+AxRvPhOXWTTz2yzq+spqjJgiiZe9ds1uvPdu uvpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Hi4KEYkOeqiZNTWr9KA2PYqFwLBCrciDgI8JaNsGQn4=; b=LVAJSvePBtk2gZ796E+Ain5dpZI7gm9jZ3FguTCotSArgYfS8W063/5TgTOv8+XpHh JcTtwL0giY9gx1GpW6U/u7JM907Uq/hWFE5+qP0Dmb2CI8R/2CyoCgH7visWXVnik056 E59qcNfBrIIAr2ctTVO05IX1B6aUjmeQWH8pjqYew37e3JyfjCZyyZHcTAFsf90UjvdB 92JVPXKA2zEHpbtGIzNz+Ka60BVR8dynhnVDRynhkd1c9eATQGePvcJOgwAJZIFOgq+6 k5YddhFe8aGmQNSrgfy+IHaQo6xg59F2G7Hw6fahSr3lxWaYnySxxorMlUkAG7qFmuA7 T7Yw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 2si8982485wms.238.2017.09.12.11.13.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 11:13:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drpgx-000180-Mu; Tue, 12 Sep 2017 19:13:47 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 12/19] nvic: In escalation to HardFault, support HF not being priority -1 Date: Tue, 12 Sep 2017 19:13:59 +0100 Message-Id: <1505240046-11454-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> References: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> When escalating to HardFault, we must go into Lockup if we can't take the synchronous HardFault because the current execution priority is already at or below the priority of HardFault. In v7M HF is always priority -1 so a simple < 0 comparison sufficed; in v8M the priority of HardFault can vary depending on whether it is a Secure or NonSecure HardFault, so we must check against the priority of the HardFault exception vector we're about to use. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 3361a28..c4670f7 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -487,18 +487,8 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) } if (escalate) { - if (running < 0) { - /* We want to escalate to HardFault but we can't take a - * synchronous HardFault at this point either. This is a - * Lockup condition due to a guest bug. We don't model - * Lockup, so report via cpu_abort() instead. - */ - cpu_abort(&s->cpu->parent_obj, - "Lockup: can't escalate %d to HardFault " - "(current priority %d)\n", irq, running); - } - /* We can do the escalation, so we take HardFault instead. + /* We need to escalate this exception to a synchronous HardFault. * If BFHFNMINS is set then we escalate to the banked HF for * the target security state of the original exception; otherwise * we take a Secure HardFault. @@ -511,6 +501,17 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) } else { vec = &s->vectors[irq]; } + if (running <= vec->prio) { + /* We want to escalate to HardFault but we can't take the + * synchronous HardFault at this point either. This is a + * Lockup condition due to a guest bug. We don't model + * Lockup, so report via cpu_abort() instead. + */ + cpu_abort(&s->cpu->parent_obj, + "Lockup: can't escalate %d to HardFault " + "(current priority %d)\n", irq, running); + } + /* HF may be banked but there is only one shared HFSR */ s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; }