From patchwork Tue Sep 12 18:14:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112360 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5549053qgf; Tue, 12 Sep 2017 11:13:49 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBAX1KIdHJh+lz9ZN6FKX6qoMxkioHV9aRtPh0O/FJ3vHx/v8AbRmWI/f49CEV/gDbWcmXj X-Received: by 10.28.10.142 with SMTP id 136mr303134wmk.92.1505240028890; Tue, 12 Sep 2017 11:13:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505240028; cv=none; d=google.com; s=arc-20160816; b=n7enjmerh66DnV35uxtfsiXH0XFXLHND64QreopJ1Sq+lWUltN+V5/2xtcuPNThQaZ yuOsdLg2nj0g+OKAtTVjEyQvPOqLedFRMVUDDSaqWMsnmVTT7ZgfMPsRkw1fJz0S6Y5C NB7Ps8WQXnY6MHBy/Q2l0kuMCv5iNskxHozU2wavUmg/Mq0gwexurM2DSiHhNCWUnXVr a5ZbXl49FIR+FNH9tMFQv2LKUtXZHKCpRafZg/RFLE/CWE6f4IGS1LrjWWfCvbzTXaBi nx5ZdBi8UU+PjWRYyP+QZCRpRIP/LVMh9YAyu+2PNoqZz2N+8KBjM+ubwilKD0DxVfuS jDkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=mg2A4zX2ZTvB3uLwahEsHqpOEORmmkpaaPSUzV5IF8w=; b=W9FBGR0TdzVefDD1XruqL/z8rfJ/5X8E5oRfdCNVeIz5jcAUjD6Hwr/5TnVq74VEtW fVNJOAt5ajn6d9wpjkULLzznwwWfswjJ3oh+anqjpizlJ4JA7dPKtwM0uQxKX8EFAOaN bVEd6nJH2EZWf15uQrEk7nJw6Nv58PwxP4pS2wxgDwIhPXMjlONmWgUfMHRuLYGPKO4n 6cvpTX1WLTxNiYw4Jj7KAA9cfvXQ1BEzUWIDTkbYGGsFx1ybCdDhq6L1HybNSBDVfEvf sC8LZmojCbaidWZahJCM1L06EEdTYjGoEKbvUVJEIA/T3+vGOmhJWqMGXhua3Eu4QfJD CE+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id p103si9515275wrc.149.2017.09.12.11.13.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 11:13:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drpgy-00018i-Ao; Tue, 12 Sep 2017 19:13:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 13/19] nvic: Implement v8M changes to fixed priority exceptions Date: Tue, 12 Sep 2017 19:14:00 +0100 Message-Id: <1505240046-11454-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> References: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> In v7M, the fixed-priority exceptions are: Reset: -3 NMI: -2 HardFault: -1 In v8M, this changes because Secure HardFault may need to be prioritised above NMI: Reset: -4 Secure HardFault if AIRCR.BFHFNMINS == 1: -3 NMI: -2 Secure HardFault if AIRCR.BFHFNMINS == 0: -1 NonSecure HardFault: -1 Make these changes, including support for changing the priority of Secure HardFault as AIRCR.BFHFNMINS changes. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c4670f7..db2f170 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -937,6 +937,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, (R_V7M_AIRCR_SYSRESETREQS_MASK | R_V7M_AIRCR_BFHFNMINS_MASK | R_V7M_AIRCR_PRIS_MASK); + /* BFHFNMINS changes the priority of Secure HardFault */ + if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { + s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3; + } else { + s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; + } } nvic_irq_update(s); } @@ -1452,9 +1458,12 @@ static int nvic_post_load(void *opaque, int version_id) { NVICState *s = opaque; unsigned i; + int resetprio; /* Check for out of range priority settings */ - if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 || + resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; + + if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || s->vectors[ARMV7M_EXCP_NMI].prio != -2 || s->vectors[ARMV7M_EXCP_HARD].prio != -1) { return 1; @@ -1497,7 +1506,12 @@ static int nvic_security_post_load(void *opaque, int version_id) int i; /* Check for out of range priority settings */ - if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) { + if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1 + && s->sec_vectors[ARMV7M_EXCP_HARD].prio != -3) { + /* We can't cross-check against AIRCR.BFHFNMINS as we don't know + * if the CPU state has been migrated yet; a mismatch won't + * cause the emulation to blow up, though. + */ return 1; } for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) { @@ -1544,6 +1558,7 @@ static Property props_nvic[] = { static void armv7m_nvic_reset(DeviceState *dev) { + int resetprio; NVICState *s = NVIC(dev); s->vectors[ARMV7M_EXCP_NMI].enabled = 1; @@ -1556,7 +1571,8 @@ static void armv7m_nvic_reset(DeviceState *dev) s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; - s->vectors[ARMV7M_EXCP_RESET].prio = -3; + resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; + s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; s->vectors[ARMV7M_EXCP_NMI].prio = -2; s->vectors[ARMV7M_EXCP_HARD].prio = -1;