From patchwork Tue Sep 12 18:14:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112361 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5549066qgf; Tue, 12 Sep 2017 11:13:49 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDGJKf19sfDMVeOC+BngeRSK63AsCgsrSTfLIFyLRSAOyyeS/PiLDRnRPinzYb11l2Dkdhs X-Received: by 10.28.137.208 with SMTP id l199mr302786wmd.123.1505240029588; Tue, 12 Sep 2017 11:13:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505240029; cv=none; d=google.com; s=arc-20160816; b=RUNTqBJnVKcCN4ee+NYYVJzyWilE3UYgyuOCZeSERIkDq/BqJ9Ax4Tyg5iTmrNwzMr cvlznPw9rmc4f9vZdlVTa6hPLNZ9qEjzD20frAq7IC6f+ZIM+zqlQ7ZCbuSa/0Byo7Nw gseLQUVAYMz5MH10+VS8hLL93toZ4ETFzdBDizLACClvAb5SM3d5SAQs40zVBAitLLp1 vRzRdFKT4BA///XbMYOthpNEIuPhmOPU5anvOhjQHkPIb1pGynBocoyvKVxYZhtM254N GjdO9qA6hOs5OntaqYw6AJAiQA552GW+cff4gTeX+MqYMCrl8Hn+g5nRH3W09DQD84dk Nuhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=1HELrp4XudSVWHWja2ay6iZ9jVuM5OnXb4hNo6vMgOI=; b=ness1FsansuHMO6RwPFgsG8rvFek4UcA8rQhm6KXJ5XcLaNSA/8ygBNPWaxUnD9Apu Z0x47hb+Ul4pM79lTUpoCRSd30sthHBWRUcYNmuq5kqzx2oJ+a8tz2aJZkiDQ64RSsCf Nk3Q5mAgtrlJDzYSj6RvfJV6BS1Dr+c90E7RCKiCtzCoY/uyzvbLGWQ0K/+cAcwLwNzX QhTRh7KAKFGIhVO24UnE87/IrazA8bC1mRF8x9sY7uzhXouIRyFQclPsLqd+J8zMQmXH dIV9xRvzNj6fQzy0nvmJ/QVLh61TZc6VJHgrIJjt66LVpCV3SJerRfMNw4clL+/NxON5 zxfQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id z80si513276wmd.264.2017.09.12.11.13.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 11:13:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drpgz-00019A-1C; Tue, 12 Sep 2017 19:13:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 14/19] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear Date: Tue, 12 Sep 2017 19:14:01 +0100 Message-Id: <1505240046-11454-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> References: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually preempt execution. The simple way to achieve this is to clear the enable bit for it, since the enable bit isn't guest visible. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index db2f170..91d2f33 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -937,11 +937,16 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, (R_V7M_AIRCR_SYSRESETREQS_MASK | R_V7M_AIRCR_BFHFNMINS_MASK | R_V7M_AIRCR_PRIS_MASK); - /* BFHFNMINS changes the priority of Secure HardFault */ + /* BFHFNMINS changes the priority of Secure HardFault, and + * allows a pending Non-secure HardFault to preempt (which + * we implement by marking it enabled). + */ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3; + s->vectors[ARMV7M_EXCP_HARD].enabled = 1; } else { s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; + s->vectors[ARMV7M_EXCP_HARD].enabled = 0; } } nvic_irq_update(s); @@ -1562,7 +1567,6 @@ static void armv7m_nvic_reset(DeviceState *dev) NVICState *s = NVIC(dev); s->vectors[ARMV7M_EXCP_NMI].enabled = 1; - s->vectors[ARMV7M_EXCP_HARD].enabled = 1; /* MEM, BUS, and USAGE are enabled through * the System Handler Control register */ @@ -1584,6 +1588,10 @@ static void armv7m_nvic_reset(DeviceState *dev) /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1; + /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */ + s->vectors[ARMV7M_EXCP_HARD].enabled = 0; + } else { + s->vectors[ARMV7M_EXCP_HARD].enabled = 1; } /* Strictly speaking the reset handler should be enabled.