From patchwork Tue Sep 12 18:14:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112364 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5549108qgf; Tue, 12 Sep 2017 11:13:51 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDxLKHCSqvBMksMhltAAqqABo+CnX8S/Z5IWLfQ4BdlqfjArjuqm4S8L0Ht9V7vL/0LQLLu X-Received: by 10.28.52.132 with SMTP id b126mr338325wma.144.1505240031860; Tue, 12 Sep 2017 11:13:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505240031; cv=none; d=google.com; s=arc-20160816; b=OPssCJkXSlqsT75lPl4fQgE9s0+cP7Of8wxQ9Kh9cn5/39Xij1dT3Oy56llBxoyMHT b65SaMzeLXorWIkZHfC/Pwxs5ipSxsAUFEuAup6zQOn1QLyAKbSvS/8jY5haN6e67dS9 1KcclKyIig2Z1EeSBGEOLxnA4Ki6Y615qv06s+ynYRTcXcT0xxkn73n38GzxkX7H7CgF IcGL2x1bQfG9rMkb7LRRzS9k5v69U/J6g5svPLkI9+0UF2+F4Obxt0j9mA13LZdg/4wX gg13gKfVvDBVjhByIalA6DSxoB9HqnwlZz9rLDS94+LpVMGQNqtMJ3+qKT2aGTbVn0zS ACCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=01dh5BWCFYErQ39khmrp+Y96B3+LsFoIqLF8Q0CFSD0=; b=awjPw+6GDotZ0FE8/bdFgnpAWDaG3Xm66rW0DJy1zYILLwuaLnnBOAVVrKQYLa6f21 NmHk/3laFZ2UbpFqWDDjdcQIHidz2nEBwCWmOGlz/JetAqXYeWbiQssSbb/SF312+F8C G/jlgjUqSFgTDU/st8pd1paBCtMgMNC3UtFkGPDQisi2SUbJOUZ+l5P5WcEf1YMsCjfX Qm9zXGBlKFmrQ/kdKm2LCVl5s2BXvLDjqdOwUv13YZ4VEV1YdbK6DzjwB/02NEHAe3O0 CbZDsTxmt45WpAKnVJZE4ulBIeIy0BegLOnChrN+LjZmS37Jcnhja+uUST7yZ344SRSr r+zA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id q30si9352383wra.109.2017.09.12.11.13.51 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 11:13:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drph1-0001AY-7j; Tue, 12 Sep 2017 19:13:51 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 17/19] nvic: Make ICSR banked for v8M Date: Tue, 12 Sep 2017 19:14:04 +0100 Message-Id: <1505240046-11454-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> References: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> The ICSR NVIC register is banked for v8M. This doesn't require any new state, but it does mean that some bits are controlled by BFHNFNMINS and some bits must work with the correct banked exception. There is also a new in v8M PENDNMICLR bit. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 45 ++++++++++++++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 13 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5e5aecd..21fd199 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -703,7 +703,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } case 0xd00: /* CPUID Base. */ return cpu->midr; - case 0xd04: /* Interrupt Control State. */ + case 0xd04: /* Interrupt Control State (ICSR) */ /* VECTACTIVE */ val = cpu->env.v7m.exception; /* VECTPENDING */ @@ -716,19 +716,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) if (nvic_rettobase(s)) { val |= (1 << 11); } - /* PENDSTSET */ - if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { - val |= (1 << 26); - } - /* PENDSVSET */ - if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { - val |= (1 << 28); + if (attrs.secure) { + /* PENDSTSET */ + if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) { + val |= (1 << 26); + } + /* PENDSVSET */ + if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) { + val |= (1 << 28); + } + } else { + /* PENDSTSET */ + if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { + val |= (1 << 26); + } + /* PENDSVSET */ + if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { + val |= (1 << 28); + } } /* NMIPENDSET */ - if (s->vectors[ARMV7M_EXCP_NMI].pending) { + if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && + s->vectors[ARMV7M_EXCP_NMI].pending) { val |= (1 << 31); } - /* ISRPREEMPT not implemented */ + /* ISRPREEMPT: RES0 when halting debug not implemented */ + /* STTNS: RES0 for the Main Extension */ return val; case 0xd08: /* Vector Table Offset. */ return cpu->env.v7m.vecbase[attrs.secure]; @@ -953,9 +966,15 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, nvic_irq_update(s); break; } - case 0xd04: /* Interrupt Control State. */ - if (value & (1 << 31)) { - armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); + case 0xd04: /* Interrupt Control State (ICSR) */ + if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { + if (value & (1 << 31)) { + armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); + } else if (value & (1 << 30) && + arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PENDNMICLR didn't exist in v7M */ + armv7m_nvic_clear_pending(s, ARMV7M_EXCP_NMI, false); + } } if (value & (1 << 28)) { armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);