From patchwork Wed Sep 13 02:05:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112394 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp373791qgf; Tue, 12 Sep 2017 19:08:16 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4k8hEDmM8eaR6E/b2L54+q7FMMxdoeN2R8HAmrqzFbqtuqN/rjAZAsCiIjfymswNFfaZnF X-Received: by 10.84.224.141 with SMTP id s13mr18867645plj.409.1505268496582; Tue, 12 Sep 2017 19:08:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505268496; cv=none; d=google.com; s=arc-20160816; b=nYCEWFP35oYpW/lEIYqobQ3j8VbVyKY9Qogf7A2KFkr8mDYzUmWmnRuzvQ7waJf5cN 9jOvUOubRdoOIu7FwqgPMt/qxpYyZ+5XdwR1v4aGX/Zmk8T1tAOkMHoY0hNGI0Sq8HyS ICzk7mIQkhIScNphxFlQ4/qCYTGgYZZtV4lW9TOnHhktJdfFLGiqgvEpKbLKTnIlI3mb uH2fM3DTVKLAkHk7Brz8v4rn95BYGHZBY9qb5tvw0aXuILMaDRIRYHdUTbg5GvyOYCYO HwQj5o1Pa2EKj+63U0PX9pcsd+BcZuzbyz+lIbGrv4XkaR/oeP1OOuRX6MTNyEUUNu/V kGNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=dhQKnl1jCWLTtqsd2XpOowPrPTsXyZWMtFdmiwfMt0g=; b=MLoWdS4sa7/5lkygrHKC6nLMqJUUNSvCDLeDJQ50IOcDcxU5T753ax0/X0d8XunNFy 7zXEJBTIKO0BiNgZI0nJe4FxmtBjDoqPefF+TQv2aFf+D02dtoCQxigIBAfP9ZP9w44S Fn/2K2tRfWhal00PnHAJEjipDVIC3C88Czy18vy78oSmTX9HrYeHsgf7AsXP124AHZEG LWshcktkWdVsCJMS/OSupwiJOYNBiTJbXz7o3LmZ1tyJUdofKxti6S9ykt09Fh/dso9T lS/4WbvOnhc0ADRUOaBHTvlE27JTCpkh9cQD8bgxuGbsK/E2amblK0iIknWyYsBqIeEY t1LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=2JGr3JU2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f15si8607800pgu.578.2017.09.12.19.08.16; Tue, 12 Sep 2017 19:08:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=2JGr3JU2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751820AbdIMCIK (ORCPT + 26 others); Tue, 12 Sep 2017 22:08:10 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:41635 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751728AbdIMCIG (ORCPT ); Tue, 12 Sep 2017 22:08:06 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v8D25uqA022945; Wed, 13 Sep 2017 11:05:57 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v8D25uqA022945 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505268358; bh=dhQKnl1jCWLTtqsd2XpOowPrPTsXyZWMtFdmiwfMt0g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2JGr3JU2M9lusOvsW166IcDns97nJXC/5jLpkYV4YDDASoVAAkhJ1Mrdwq4p3+GaJ wLtocxjU2r8yv9EXM5RZaikpVsXgJAtDLKncYboyLijpM48K7urBycwwME5eTu1NvU Dl/2feP1fAzlCVaXhruxK8FNMldKMguL+hbfT11Qm158cjLW5qE1WuN151ojStZtwO 3GsJ+OAApyhNm9SlTTYBn9S/qut1p2fmO7ftLE+oBeKlHSFrRu1eFa5Slbnx77NPAm 0OFSCqTf92wXhyblO2w6DTqsp/vE4F49BQFpIp1bVaEV3IsR6BEP8hQIdCTjMEBPBx 5+iVPVQOeGdqA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , Josh Wu , Wan ZongShun , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse , Wenyou Yang , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag Date: Wed, 13 Sep 2017 11:05:50 +0900 Message-Id: <1505268351-31941-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505268351-31941-1-git-send-email-yamada.masahiro@socionext.com> References: <1505268351-31941-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Several drivers check ->chipsize to see if the third row address cycle is needed. Instead of embedding magic sizes such as 32MB, 128MB in drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since nand_scan_ident() knows well about the device, it can handle this properly. The flag is set if the row address bit width is greater than 16. Delete comments such as "One more address cycle for ..." because intention is now clear enough from the code. Signed-off-by: Masahiro Yamada --- Changes in v2: - Fix build error drivers/mtd/nand/atmel/nand-controller.c | 3 +-- drivers/mtd/nand/au1550nd.c | 3 +-- drivers/mtd/nand/diskonchip.c | 3 +-- drivers/mtd/nand/hisi504_nand.c | 3 +-- drivers/mtd/nand/mxc_nand.c | 3 +-- drivers/mtd/nand/nand_base.c | 9 +++++---- drivers/mtd/nand/nuc900_nand.c | 2 +- include/linux/mtd/rawnand.h | 3 +++ 8 files changed, 14 insertions(+), 15 deletions(-) -- 2.7.4 Acked-by: Wenyou Yang diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c index f25eca7..7bc8d20 100644 --- a/drivers/mtd/nand/atmel/nand-controller.c +++ b/drivers/mtd/nand/atmel/nand-controller.c @@ -718,8 +718,7 @@ static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column) nc->op.addrs[nc->op.naddrs++] = page; nc->op.addrs[nc->op.naddrs++] = page >> 8; - if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) || - (mtd->writesize <= 512 && chip->chipsize > SZ_32M)) + if (chip->options & NAND_ROW_ADDR_3) nc->op.addrs[nc->op.naddrs++] = page >> 16; } } diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 9d4a28f..8ab827e 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -331,8 +331,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i ctx->write_byte(mtd, (u8)(page_addr >> 8)); - /* One more address cycle for devices > 32MiB */ - if (this->chipsize > (32 << 20)) + if (this->options & NAND_ROW_ADDR_3) ctx->write_byte(mtd, ((page_addr >> 16) & 0x0f)); } diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c index c3aa53c..72671dc 100644 --- a/drivers/mtd/nand/diskonchip.c +++ b/drivers/mtd/nand/diskonchip.c @@ -705,8 +705,7 @@ static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int colu if (page_addr != -1) { WriteDOC((unsigned char)(page_addr & 0xff), docptr, Mplus_FlashAddress); WriteDOC((unsigned char)((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress); - /* One more address cycle for higher density devices */ - if (this->chipsize & 0x0c000000) { + if (this->options & NAND_ROW_ADDR_3) { WriteDOC((unsigned char)((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress); printk("high density\n"); } diff --git a/drivers/mtd/nand/hisi504_nand.c b/drivers/mtd/nand/hisi504_nand.c index d9ee1a7..0897261 100644 --- a/drivers/mtd/nand/hisi504_nand.c +++ b/drivers/mtd/nand/hisi504_nand.c @@ -432,8 +432,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr) host->addr_value[0] |= (page_addr & 0xffff) << (host->addr_cycle * 8); host->addr_cycle += 2; - /* One more address cycle for devices > 128MiB */ - if (chip->chipsize > (128 << 20)) { + if (chip->options & NAND_ROW_ADDR_3) { host->addr_cycle += 1; if (host->command == NAND_CMD_ERASE1) host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 53e5e03..bacdd04 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -859,8 +859,7 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) host->devtype_data->send_addr(host, (page_addr >> 8) & 0xff, true); } else { - /* One more address cycle for higher density devices */ - if (mtd->size >= 0x4000000) { + if (nand_chip->options & NAND_ROW_ADDR_3) { /* paddr_8 - paddr_15 */ host->devtype_data->send_addr(host, (page_addr >> 8) & 0xff, diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index bcc8cef1..3bc4404 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -727,8 +727,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, chip->cmd_ctrl(mtd, page_addr, ctrl); ctrl &= ~NAND_CTRL_CHANGE; chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); - /* One more address cycle for devices > 32MiB */ - if (chip->chipsize > (32 << 20)) + if (chip->options & NAND_ROW_ADDR_3) chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); } chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); @@ -854,8 +853,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, chip->cmd_ctrl(mtd, page_addr, ctrl); chip->cmd_ctrl(mtd, page_addr >> 8, NAND_NCE | NAND_ALE); - /* One more address cycle for devices > 128MiB */ - if (chip->chipsize > (128 << 20)) + if (chip->options & NAND_ROW_ADDR_3) chip->cmd_ctrl(mtd, page_addr >> 16, NAND_NCE | NAND_ALE); } @@ -4000,6 +3998,9 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) chip->chip_shift += 32 - 1; } + if (chip->chip_shift - chip->page_shift > 16) + chip->options |= NAND_ROW_ADDR_3; + chip->badblockbits = 8; chip->erase = single_erase; diff --git a/drivers/mtd/nand/nuc900_nand.c b/drivers/mtd/nand/nuc900_nand.c index 7bb4d2e..af5b32c9 100644 --- a/drivers/mtd/nand/nuc900_nand.c +++ b/drivers/mtd/nand/nuc900_nand.c @@ -154,7 +154,7 @@ static void nuc900_nand_command_lp(struct mtd_info *mtd, unsigned int command, if (page_addr != -1) { write_addr_reg(nand, page_addr); - if (chip->chipsize > (128 << 20)) { + if (chip->options & NAND_ROW_ADDR_3) { write_addr_reg(nand, page_addr >> 8); write_addr_reg(nand, page_addr >> 16 | ENDADDR); } else { diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 2b05f42..749bb08 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -177,6 +177,9 @@ enum nand_ecc_algo { */ #define NAND_NEED_SCRAMBLING 0x00002000 +/* Device needs 3rd row address cycle */ +#define NAND_ROW_ADDR_3 0x00004000 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG