[v7,1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801

Message ID 20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com
State New
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Series
  • iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)
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Commit Message

Shameer Kolothum Sept. 14, 2017, 12:57 p.m.
From: John Garry <john.garry@huawei.com>


The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms
hip06/hip07 to support the SMMU mappings for MSI transactions.

On these platforms, GICv3 ITS translator is presented with the deviceID
by extending the MSI payload data to 64 bits to include the deviceID.
Hence, the PCIe controller on this platforms has to differentiate the MSI
payload against other DMA payload and has to modify the MSI payload.
This basically makes it difficult for this platforms to have a SMMU
translation for MSI.

This patch adds a SMMUv3 binding to flag that the SMMU breaks msi
translation at ITS.

Also, the arm64 silicon errata is updated with this same erratum.

Signed-off-by: John Garry <john.garry@huawei.com>

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---
 Documentation/arm64/silicon-errata.txt                  | 1 +
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 3 +++
 2 files changed, 4 insertions(+)

-- 
1.9.1


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Patch

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 66e8ce1..02816b1 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -70,6 +70,7 @@  stable kernels.
 |                |                 |                 |                             |
 | Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |
 | Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |
+| Hisilicon      | Hip0{6,7}       | #161010801      | N/A                         |
 |                |                 |                 |                             |
 | Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 | Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
index c9abbf3..1f5f7f9 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
@@ -55,6 +55,9 @@  the PCIe specification.
 - hisilicon,broken-prefetch-cmd
                     : Avoid sending CMD_PREFETCH_* commands to the SMMU.
 
+- hisilicon,broken-untranslated-msi
+                    : Reserve ITS HW region to avoid translating msi.
+
 - cavium,cn9900-broken-page1-regspace
                     : Replaces all page 1 offsets used for EVTQ_PROD/CONS,
 		      PRIQ_PROD/CONS register access with page 0 offsets.