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[209.132.180.67]) by mx.google.com with ESMTP id a59si4681282plc.638.2017.09.18.02.02.44; Mon, 18 Sep 2017 02:02:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UjJYgVxJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752830AbdIRJCm (ORCPT + 6 others); Mon, 18 Sep 2017 05:02:42 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:48648 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752829AbdIRJC3 (ORCPT ); Mon, 18 Sep 2017 05:02:29 -0400 Received: by mail-wm0-f47.google.com with SMTP id r68so635623wmg.3 for ; Mon, 18 Sep 2017 02:02:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G5YIS7hIBYSgFWZ67w6lo4uUDWPfdt4dfSo7J/z81lU=; b=UjJYgVxJHL5Z57xPlVGFEYWbLF32Acm2wxF893Mb+W8qYauS7OrPFMsNq/GOch3dsF tPNg0Y6qwNsylSMOo/bB0sLYwUBBxH0hwBV6VV4wU4lKREpWZFIP9hofighxXrAV9/yG lk/7Q3sgq+2vCnydhoilasJE8h6lX8veLbUPM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G5YIS7hIBYSgFWZ67w6lo4uUDWPfdt4dfSo7J/z81lU=; b=CmbEw/D496YAF+DPDfdDAyrd0b4jEEOoO4HdqhWayUGDilpMfq07FvM/2oYaZwX2UY 8uB1YW5HUk1iOmo4ujAYFtO8YgYJP3yuiba+GvQdFRrtQOY9QIEIFjeTdXCshV4fXk4Q Bk6BreU3YO3wRkEfmw8+9GJZUyvGrwfCJAPV07EHPZ0eQY/7gr/5fh11Ts1YywD+0tBP wta/5OvwF1omu0j6rhdTkAFzK6zIiM5U4p7as14Esoak8TLf0gbjZZ63eU4+I4YcQ9lV /slHw3hZcJ8jCYDE7ywbpUptPrfly7TwyvN8vBB7p1IElbTZiozk5qe3nJDzyc4mSFpn BTgA== X-Gm-Message-State: AHPjjUjkkgJSI+23+vzy/rYwXfJADSNCzDpJwnMP6nG3FD0Zu7relbjT +Gn5UhtAtyz4xQmDd6jBKw== X-Google-Smtp-Source: AOwi7QC8SWxcN7nI1zXCl7IC8sUvwUIEDIW1Vjvum0xGVEg7JJimBnvgPjEg0dub2JYsqYuQYjNSuw== X-Received: by 10.28.66.65 with SMTP id p62mr8516654wma.159.1505725347893; Mon, 18 Sep 2017 02:02:27 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.214.127.140]) by smtp.gmail.com with ESMTPSA id p80sm6201554wmf.42.2017.09.18.02.02.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Sep 2017 02:02:27 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v2 2/2] arm: dts: stm32: remove useless clocksource nodes Date: Mon, 18 Sep 2017 11:02:15 +0200 Message-Id: <1505725335-27081-3-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505725335-27081-1-git-send-email-benjamin.gaignard@linaro.org> References: <1505725335-27081-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 16 bits timers aren't accurate enough to be used as clocksource, remove them from stm32f4 and stm32f7 devicetree. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index a8113dc..fd211cb 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -108,14 +108,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -137,14 +129,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +178,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +194,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 4506eb9..c4d0273 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,22 +82,6 @@ status = "disabled"; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,22 +89,6 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>;