arm64: dts: foundation-v8: Enable PSCI mode

Message ID 20170918153832.16356-1-daniel.thompson@linaro.org
State New
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Series
  • arm64: dts: foundation-v8: Enable PSCI mode
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Commit Message

Daniel Thompson Sept. 18, 2017, 3:38 p.m.
Currently if the Foundation model is running ARM Trusted Firmware then
the kernel, which is configured to use spin tables, cannot start secondary
processors or "power off" the simulation.

Add a couple of labels to the include file, and introduce a new .dts
file that uses these to override the enable-method.

Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>

---
 arch/arm64/boot/dts/arm/Makefile                   |  3 +-
 .../boot/dts/arm/foundation-v8-gicv3-psci.dts      | 51 ++++++++++++++++++++++
 arch/arm64/boot/dts/arm/foundation-v8.dtsi         |  8 ++--
 3 files changed, 57 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts

--
2.9.5

Comments

Mark Rutland Sept. 18, 2017, 4:12 p.m. | #1
Hi Daniel,

On Mon, Sep 18, 2017 at 04:38:32PM +0100, Daniel Thompson wrote:
> Currently if the Foundation model is running ARM Trusted Firmware then

> the kernel, which is configured to use spin tables, cannot start secondary

> processors or "power off" the simulation.

> 

> Add a couple of labels to the include file, and introduce a new .dts

> file that uses these to override the enable-method.

> 

> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>


This looks good, but has the unfortunate effect of leaving the
(irrelevant) cpu-release-addr property in the PSCI dts files, as that's
in the underlying dtsi file.

Could we split spin-table / PSCI parts into separate dtsi files?

e.g. have:

* foundation-v8.dtsi
* foundation-v8-gicv{2,3}.dtsi
* foundation-v8-{psci,spin-table}.dtsi

... and then combine those to build the dts files we want.

FWIW, with that:

Acked-by: Mark Rutland <mark.rutland@arm.com>


Thanks,
Mark.
Daniel Thompson Sept. 19, 2017, 3:59 p.m. | #2
On 18/09/17 17:12, Mark Rutland wrote:
> Hi Daniel,

> 

> On Mon, Sep 18, 2017 at 04:38:32PM +0100, Daniel Thompson wrote:

>> Currently if the Foundation model is running ARM Trusted Firmware then

>> the kernel, which is configured to use spin tables, cannot start secondary

>> processors or "power off" the simulation.

>>

>> Add a couple of labels to the include file, and introduce a new .dts

>> file that uses these to override the enable-method.

>>

>> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>

> 

> This looks good, but has the unfortunate effect of leaving the

> (irrelevant) cpu-release-addr property in the PSCI dts files, as that's

> in the underlying dtsi file.

> 

> Could we split spin-table / PSCI parts into separate dtsi files?

> 

> e.g. have:

> 

> * foundation-v8.dtsi

> * foundation-v8-gicv{2,3}.dtsi

> * foundation-v8-{psci,spin-table}.dtsi

> 

> ... and then combine those to build the dts files we want.


Will do.

> 

> FWIW, with that:

> 

> Acked-by: Mark Rutland <mark.rutland@arm.com>


Talking about what we want... if it's all split out I might as well add 
a gicv2+psci DT as well. Will that still retain your Acked-by or do you 
want to see it first ;-) ?


Daniel.
Mark Rutland Sept. 19, 2017, 4:20 p.m. | #3
On Tue, Sep 19, 2017 at 04:59:15PM +0100, Daniel Thompson wrote:
> On 18/09/17 17:12, Mark Rutland wrote:


> >Could we split spin-table / PSCI parts into separate dtsi files?

> >

> >e.g. have:

> >

> >* foundation-v8.dtsi

> >* foundation-v8-gicv{2,3}.dtsi

> >* foundation-v8-{psci,spin-table}.dtsi

> >

> >... and then combine those to build the dts files we want.

> 

> Will do.

> 

> >FWIW, with that:

> >

> >Acked-by: Mark Rutland <mark.rutland@arm.com>

> 

> Talking about what we want... if it's all split out I might as well

> add a gicv2+psci DT as well. Will that still retain your Acked-by or

> do you want to see it first ;-) ?


Sure; that's fine by me. :)

Thanks,
Mark.

Patch

diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index 75cc2aa10101..c9ec88809f3d 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -1,4 +1,5 @@ 
-dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += \
+	foundation-v8.dtb foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts b/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts
new file mode 100644
index 000000000000..94a249095104
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts
@@ -0,0 +1,51 @@ 
+/*
+ * ARM Ltd.
+ *
+ * ARMv8 Foundation model DTS (GICv3 configuration)
+ */
+
+#include "foundation-v8.dtsi"
+
+/ {
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	gic: interrupt-controller@2f000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+		reg =	<0x0 0x2f000000 0x0 0x10000>,
+			<0x0 0x2f100000 0x0 0x200000>,
+			<0x0 0x2c000000 0x0 0x2000>,
+			<0x0 0x2c010000 0x0 0x2000>,
+			<0x0 0x2c02f000 0x0 0x2000>;
+		interrupts = <1 9 4>;
+
+		its: its@2f020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x2f020000 0x0 0x20000>;
+		};
+	};
+};
+
+&cpu0 {
+	enable-method = "psci";
+};
+
+&cpu1 {
+	enable-method = "psci";
+};
+
+&cpu2 {
+	enable-method = "psci";
+};
+
+&cpu3 {
+	enable-method = "psci";
+};
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index 8ecdd4331980..8c7f8c4f090a 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -28,7 +28,7 @@ 
 		#address-cells = <2>;
 		#size-cells = <0>;

-		cpu@0 {
+		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x0>;
@@ -36,7 +36,7 @@ 
 			cpu-release-addr = <0x0 0x8000fff8>;
 			next-level-cache = <&L2_0>;
 		};
-		cpu@1 {
+		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x1>;
@@ -44,7 +44,7 @@ 
 			cpu-release-addr = <0x0 0x8000fff8>;
 			next-level-cache = <&L2_0>;
 		};
-		cpu@2 {
+		cpu2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x2>;
@@ -52,7 +52,7 @@ 
 			cpu-release-addr = <0x0 0x8000fff8>;
 			next-level-cache = <&L2_0>;
 		};
-		cpu@3 {
+		cpu3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x3>;