| Message ID | 87o9q8ezad.fsf@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [AArch64] PR71307: Define union class of POINTER+FP | expand |
On 18/09/17 17:39, Richard Sandiford wrote: > ALL_REGS doesn't function as a union class of POINTER_REGS and FP_REGS > since it includes the CC register as well. REGNO_REG_CLASS (CC_REGNUM) > is NO_REGS, but of course NO_REGS rightly doesn't include CC_REGNUM. > > Adding a union class for POINTER+FP allows the RA to use it as the > preferred or alternative class of a pseudo. It also works as a > union class of GENERAL+FP for modes that aren't allowed in SP. > > This is also needed for the SVE port, which adds predicate registers > to the mix. > > The combination of r252033 and this patch fixes PR71307. Tested on > aarch64-linux-gnu. Also tested on SPEC2k6, where there were no > differences outside the (mostly low) noise. OK to install? > > The main potential disadvantage I can see is that the -fsched-pressure > code isn't very good at handling union classes: it generally just updates > one pressure class for each pseudo. I haven't found any specific examples > of that causing problems though. > > Thanks, > Richard > > > 2017-09-15 Richard Sandiford <richard.sandiford@linaro.org> > Alan Hayward <alan.hayward@arm.com> > David Sherwood <david.sherwood@arm.com> > > gcc/ > PR target/71307 > * config/aarch64/aarch64.h (POINTER_AND_FP_REGS): New reg class. > (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly. > * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle > POINTER_AND_FP_REGS. > > gcc/testsuite/ > PR target/71307 > * gcc.target/aarch64/vect_copy_lane_1.c: Remove XFAIL. OK. R. > > Index: gcc/config/aarch64/aarch64.h > =================================================================== > --- gcc/config/aarch64/aarch64.h 2017-09-15 14:47:33.167333414 +0100 > +++ gcc/config/aarch64/aarch64.h 2017-09-18 17:31:34.720209011 +0100 > @@ -452,6 +452,7 @@ enum reg_class > POINTER_REGS, > FP_LO_REGS, > FP_REGS, > + POINTER_AND_FP_REGS, > ALL_REGS, > LIM_REG_CLASSES /* Last */ > }; > @@ -467,6 +468,7 @@ #define REG_CLASS_NAMES \ > "POINTER_REGS", \ > "FP_LO_REGS", \ > "FP_REGS", \ > + "POINTER_AND_FP_REGS", \ > "ALL_REGS" \ > } > > @@ -479,6 +481,7 @@ #define REG_CLASS_CONTENTS \ > { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ > { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ > { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ > + { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ > { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ > } > > Index: gcc/config/aarch64/aarch64.c > =================================================================== > --- gcc/config/aarch64/aarch64.c 2017-09-18 14:58:24.012256423 +0100 > +++ gcc/config/aarch64/aarch64.c 2017-09-18 17:31:34.720209011 +0100 > @@ -6009,6 +6009,7 @@ aarch64_class_max_nregs (reg_class_t reg > case POINTER_REGS: > case GENERAL_REGS: > case ALL_REGS: > + case POINTER_AND_FP_REGS: > case FP_REGS: > case FP_LO_REGS: > return > Index: gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c > =================================================================== > --- gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c 2016-11-22 21:16:00.000000000 +0000 > +++ gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c 2017-09-18 17:31:34.720209011 +0100 > @@ -45,8 +45,7 @@ BUILD_TEST (uint32x2_t, uint32x4_t, , > BUILD_TEST (float64x1_t, float64x2_t, , q, f64, 0, 1) > BUILD_TEST (int64x1_t, int64x2_t, , q, s64, 0, 1) > BUILD_TEST (uint64x1_t, uint64x2_t, , q, u64, 0, 1) > -/* XFAIL due to PR 71307. */ > -/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 { xfail *-*-* } } } */ > +/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 } } */ > > /* vcopyq_lane. */ > BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7) >
Index: gcc/config/aarch64/aarch64.h =================================================================== --- gcc/config/aarch64/aarch64.h 2017-09-15 14:47:33.167333414 +0100 +++ gcc/config/aarch64/aarch64.h 2017-09-18 17:31:34.720209011 +0100 @@ -452,6 +452,7 @@ enum reg_class POINTER_REGS, FP_LO_REGS, FP_REGS, + POINTER_AND_FP_REGS, ALL_REGS, LIM_REG_CLASSES /* Last */ }; @@ -467,6 +468,7 @@ #define REG_CLASS_NAMES \ "POINTER_REGS", \ "FP_LO_REGS", \ "FP_REGS", \ + "POINTER_AND_FP_REGS", \ "ALL_REGS" \ } @@ -479,6 +481,7 @@ #define REG_CLASS_CONTENTS \ { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ + { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ } Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-09-18 14:58:24.012256423 +0100 +++ gcc/config/aarch64/aarch64.c 2017-09-18 17:31:34.720209011 +0100 @@ -6009,6 +6009,7 @@ aarch64_class_max_nregs (reg_class_t reg case POINTER_REGS: case GENERAL_REGS: case ALL_REGS: + case POINTER_AND_FP_REGS: case FP_REGS: case FP_LO_REGS: return Index: gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c 2016-11-22 21:16:00.000000000 +0000 +++ gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c 2017-09-18 17:31:34.720209011 +0100 @@ -45,8 +45,7 @@ BUILD_TEST (uint32x2_t, uint32x4_t, , BUILD_TEST (float64x1_t, float64x2_t, , q, f64, 0, 1) BUILD_TEST (int64x1_t, int64x2_t, , q, s64, 0, 1) BUILD_TEST (uint64x1_t, uint64x2_t, , q, u64, 0, 1) -/* XFAIL due to PR 71307. */ -/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "dup\\td0, v1.d\\\[1\\\]" 3 } } */ /* vcopyq_lane. */ BUILD_TEST (poly8x16_t, poly8x8_t, q, , p8, 15, 7)