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[54.225.227.206]) by mx.google.com with ESMTP id r46si1392582qtb.243.2017.09.19.07.09.39; Tue, 19 Sep 2017 07:09:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D8A3E62C7E; Tue, 19 Sep 2017 14:09:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 2E5A060F34; Tue, 19 Sep 2017 14:09:32 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8B9F462D05; Tue, 19 Sep 2017 14:05:33 +0000 (UTC) Received: from mail-pf0-f177.google.com (mail-pf0-f177.google.com [209.85.192.177]) by lists.linaro.org (Postfix) with ESMTPS id 7E11462C5C for ; Tue, 19 Sep 2017 14:05:02 +0000 (UTC) Received: by mail-pf0-f177.google.com with SMTP id r68so39066pfj.3 for ; Tue, 19 Sep 2017 07:05:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QX2dgutI+nFskJkoF1cilb/q8OTH+RxDAazfmAHRDfc=; b=InESJm8mAgiZpsx+GWb+mJmlDe1YYEFNNeF1WcIQNoADLItSI50MKYfKPR89S6nNZt i3AIE18qr4xtoiA+DwPNqM78Y4wlbeK9GFyl9fbrY7oiuX/o8NhtX+OIKAX0odqfuxv9 JGIXDfM7U2XFUuMFWhAC8wH36y3x8jqdXEbm2czS+VeJ3FoX9CE3WsLEq7huBqQAvOw3 j/y6vJaykLbEOfk/ohwcokBqCcuffzB9iEPD2TtDPaxlgGrLunonjuatRUsN+JZkHh3o ioNFkYf1f4+Ib1XPgnUTp5i5WXZ5vnr4U6Y/Xu0yXkEXq0s5VEjPMXbKx+OTkQ9QJ6Sx tL9w== X-Gm-Message-State: AHPjjUjRLI/4ZAIkYQWkduGWMCMnugywAktmbIoowvi94yc7cXNR/SSW bO4C4sVjnFEvi3XQ0wQ7+Nsjsmgd X-Google-Smtp-Source: AOwi7QDHCFSbKf3NCTDgWEI03KSJQe/wiMOiAR5C1QnQWWtO6uX755ryAyW6qIz13jEgWtIlWa8+Yg== X-Received: by 10.98.74.217 with SMTP id c86mr1395884pfj.225.1505829901413; Tue, 19 Sep 2017 07:05:01 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.04.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:00 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:09 +0800 Message-Id: <1505829398-52214-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: guoheyi@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 03/32] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang Change-Id: I23f987b24e284fc2e2c3c3270b32acd80052b284 --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 29 ++++++++++++++-------- .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 +++++++++-- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..6ecc1e5 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType = 1; Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE Device Iobar address should be based on IoBase */ + Ptr->AddrRangeMin = RootBridgeInstance->IoBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..8dfb4b9 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index = 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; + switch (Index) { + case TypeIo: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase; + break; + case TypeBus: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; + break; + default: + /* PCIE Device bar address should be base on PciRegionBase */ + Configuration.SpaceDesp[Index].AddrRangeMin = (PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase) + + (PrivateData->PciRegionBase & 0xFFFFFFFFFFFFFFFF); + } + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; } }