[Linaro-uefi,linaro-uefi,v1,09/32] D05/PCIe: Modify PcieRegionBase of secondary chip

Message ID 1505829398-52214-10-git-send-email-heyi.guo@linaro.org
State New
Headers show
Series
  • Update D03/D05 binary for edk update and fix some error.
Related show

Commit Message

Guo Heyi Sept. 19, 2017, 1:56 p.m.
From: huangming <huangming23@huawei.com>

On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ming Huang <huangming23@huawei.com>
---
 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl |  8 ++++----
 Platforms/Hisilicon/D05/D05.dsc                      | 12 ++++++------
 2 files changed, 10 insertions(+), 10 deletions(-)

Patch

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
index 79267e5..55c7f50 100644
--- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -646,10 +646,10 @@  Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0x20000000, // Min Base Address
+          0x40000000, // Min Base Address
           0xefffffff, // Max Base Address
           0x65000000000, // Translate
-          0xd0000000 // Length
+          0xb0000000 // Length
         )
         QWordIO (
           ResourceProducer,
@@ -766,10 +766,10 @@  Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0x30000000, // Min Base Address
+          0x40000000, // Min Base Address
           0xefffffff, // Max Base Address
           0x75000000000, // Translate
-          0xc0000000 // Length
+          0xb0000000 // Length
         )
         QWordIO (
           ResourceProducer,
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc
index 2fa0508..ffa1897 100644
--- a/Platforms/Hisilicon/D05/D05.dsc
+++ b/Platforms/Hisilicon/D05/D05.dsc
@@ -328,12 +328,12 @@ 
   gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
   gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
   gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
-  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
-  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xafffffff
   gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
   gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
-  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
-  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xafffffff
   gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
   gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
   gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
@@ -351,9 +351,9 @@ 
   gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
   gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
   gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
-  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000
   gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
-  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000
   gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
   gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
   gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000