[Linaro-uefi,linaro-uefi,v1,06/32] Hisilicon D05: Uncore PMU: Add L3 cache, MN PMU devices and properties

Message ID 1505829398-52214-7-git-send-email-heyi.guo@linaro.org
State New
Headers show
Series
  • Update D03/D05 binary for edk update and fix some error.
Related show

Commit Message

Guo Heyi Sept. 19, 2017, 1:56 p.m.
From: Chenhui Sun <sunchenhui@huawei.com>

1) The Hisilicon SoC uncore PMU devices like L3 cache, MN etc are
   probed by djtag. The djtag will have _HID and L3 cache and MN
   will use _ADR and _CID to identity the hardware version.
2) Use QWordMemory to support 64-bit address of CPU sysctrl.
3) Include UncorePMU asl in Hi1616 Dsdt.

Signed-off-by: Anurup M <anurup.m@huawei.com>
---
 .../Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl     | 385 +++++++++++++++++++++
 .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl       |   1 +
 2 files changed, 386 insertions(+)
 create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl

Patch

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl
new file mode 100644
index 0000000..d2a1432
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl
@@ -0,0 +1,385 @@ 
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2017, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2017, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB) {
+  // Djtag for CPU die #1 (scl #1)
+  Device (DJT0) {
+    Name (_HID, "HISI0202")  // _HID: Hardware ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory ( // CPU die sysctrl memory region
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        Cacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40010000, // Min Base Address
+        0x4001FFFF, // Max Base Address
+        0x0, // Translate
+        0x10000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x01}
+      }
+    })
+
+    // L3C Bank 0 for SCL #1
+    Device (L3C0) {
+      Name (_ADR, 0)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x01, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 1 for SCL #1
+    Device (L3C1) {
+      Name (_ADR, 1)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x02, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 2 for SCL #1
+    Device (L3C2) {
+      Name (_ADR, 2)
+      Name (_CID, "HISI0212")
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x03, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 3 for SCL #1
+    Device (L3C3) {
+      Name (_ADR, 3)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x04, 0x01}},
+        }
+      })
+    }
+
+    // MN1 for SCL #1
+    Device (MN1) {
+      Name (_ADR, 4)
+      Name (_CID, "HISI0222")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", 0x21},
+        }
+      })
+    }
+  }
+
+  // Djtag for CPU die #2 (scl #3)
+  Device (DJT1) {
+    Name (_HID, "HISI0202")  // _HID: Hardware ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory ( // CPU die sysctrl memory region
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        Cacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x60010000, // Min Base Address
+        0x6001FFFF, // Max Base Address
+        0x0, // Translate
+        0x10000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x03},
+		}
+    })
+
+    // L3C Bank 0 for SCL #3
+    Device (L3C0) {
+      Name (_ADR, 0)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x01, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 1 for SCL #3
+    Device (L3C1) {
+      Name (_ADR, 1)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x02, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 2 for SCL #3
+    Device (L3C2) {
+      Name (_ADR, 2)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x03, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 3 for SCL #3
+    Device (L3C3) {
+      Name (_ADR, 3)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x04, 0x01}},
+        }
+      })
+    }
+
+    // MN1 for SCL #3
+    Device (MN1) {
+      Name (_ADR, 4)
+	   Name (_CID, "HISI0222")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", 0x21},
+        }
+      })
+    }
+  }
+
+  // Djtag for CPU die #3 (scl #5)
+  Device (DJT2) {
+    Name (_HID, "HISI0202")  // _HID: Hardware ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory ( // CPU die sysctrl memory region
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        Cacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40040010000, // Min Base Address
+        0x4004001FFFF, // Max Base Address
+        0x0, // Translate
+        0x10000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x05}
+      }
+    })
+
+    // L3C Bank 0 for SCL #5
+    Device (L3C0) {
+      Name (_ADR, 0)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x01, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 1 for SCL #5
+    Device (L3C1) {
+      Name (_ADR, 1)
+      Name (_CID, "HISI0212")
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x02, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 2 for SCL #5
+    Device (L3C2) {
+      Name (_ADR, 2)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x03, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 3 for SCL #5
+    Device (L3C3) {
+      Name (_ADR, 3)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x04, 0x01}},
+        }
+      })
+    }
+
+    // MN1 for SCL #5
+    Device (MN1) {
+      Name (_ADR, 4)
+      Name (_CID, "HISI0222")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", 0x21},
+        }
+      })
+    }
+  }
+
+  // Djtag for CPU die #4 (scl #7)
+  Device (DJT3) {
+    Name (_HID, "HISI0202")  // _HID: Hardware ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory ( // CPU die sysctrl memory region
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        Cacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40060010000, // Min Base Address
+        0x4006001FFFF, // Max Base Address
+        0x0, // Translate
+        0x10000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x07}
+      }
+    })
+
+    // L3C Bank 0 for SCL #7
+    Device (L3C0) {
+      Name (_ADR, 0)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x01, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 1 for SCL #7
+    Device (L3C1) {
+      Name (_ADR, 1)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x02, 0x01}},
+        }
+      })
+    }
+
+    // L3C Bank 2 for SCL #7
+    Device (L3C2) {
+      Name (_ADR, 2)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x03, 0x01}},
+        }
+      })
+	}
+	
+    // L3C Bank 3 for SCL #7
+    Device (L3C3) {
+      Name (_ADR, 3)
+      Name (_CID, "HISI0212")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", Package () {0x04, 0x01}},
+        }
+      })
+    }
+
+    // MN1 for SCL #7
+    Device (MN1) {
+      Name (_ADR, 4)
+      Name (_CID, "HISI0222")
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"hisilicon,module-id", 0x21},
+        }
+      })
+    }
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl
index b4fc538..e4928b6 100644
--- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl
@@ -28,4 +28,5 @@  DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI  ", "HIP07   ", EFI_ACPI_ARM_O
   include ("D05Hns.asl")
   include ("D05Sas.asl")
   include ("D05Pci.asl")
+  include ("D05UncorePmu.asl")
 }