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[54.225.227.206]) by mx.google.com with ESMTP id l27si9681768qtl.35.2017.09.19.07.11.57; Tue, 19 Sep 2017 07:11:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E079E64482; Tue, 19 Sep 2017 14:11:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0614762D05; Tue, 19 Sep 2017 14:09:52 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 62AE862C62; Tue, 19 Sep 2017 14:05:41 +0000 (UTC) Received: from mail-pf0-f178.google.com (mail-pf0-f178.google.com [209.85.192.178]) by lists.linaro.org (Postfix) with ESMTPS id 487C362C60 for ; Tue, 19 Sep 2017 14:05:07 +0000 (UTC) Received: by mail-pf0-f178.google.com with SMTP id u12so36897pfl.4 for ; Tue, 19 Sep 2017 07:05:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g1gFMr+4zw1RO8pwrg+vOHFUF0Ph+Gloq2CjyE+14nY=; b=erUwDjs3Dv9prMwVVf7I/SF7bcTfttuMunqFqymzrJ8bs0n3XXTLrIF0BG7sVxc0nf nNuIHlWgYan4x+ISv3U2EjwTublw1EnsgceImO5E3oROB5K+WHlqCkATXNvAriCDQBiJ pWlkeOKgNGNSkotSUU3JW7PPnCdUw97+S75oJU86YPfbvFWz99fhDNF7aHdqBaXjqp+L 4TzwnwmU4y34CF6wSOMz0eBf4WQP0hJsUOUBjJnKKQIb0AV/LS3M3YKnQ7K/k597G707 Pw8J6a3tnWkQ0Ib/9rhdWQEicWOkwf/yRXsODzUsrSTBU4kCCz39qqAhyxC1GnepW2VJ zORg== X-Gm-Message-State: AHPjjUiXG+XyE/09FYAC8ZybbVKfMRTuLylKe5at+L6EYid7VXCJ696A AIbTHKW8ledGomZWbTdrTmyx5w/I X-Google-Smtp-Source: AOwi7QBa+MPslHdg8H3oFh5IhJhkuWimCEGR6CfbLZFTjcDNAn6RDc9V+UH8W11GJbqT03vVIN+Z1g== X-Received: by 10.98.48.194 with SMTP id w185mr1438701pfw.231.1505829906493; Tue, 19 Sep 2017 07:05:06 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:05 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:11 +0800 Message-Id: <1505829398-52214-6-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, Anurup M , guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 05/32] Hisilicon/D03: Uncore PMU Add L3 cache, MN PMU devices and properties.eml X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun The Hisilicon SoC uncore PMU devices like L3 cache, MN etc are probed by djtag. The djtag will have _HID and L3 cache and MN will use _ADR and _CID to identity the hardware version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Anurup M --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl | 204 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 2 + 2 files changed, 206 insertions(+) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl new file mode 100644 index 0000000..6d07475 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl @@ -0,0 +1,204 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) { + // Djtag for CPU die #1 (scl #1) + Device (DJT0) { + Name (_HID, "HISI0201") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40010000, // Min Base Address + 0x4001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01} + } + }) + + // L3C Bank 0 for SCL #1 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x02}}, + } + }) + } + + // L3C Bank 1 for SCL #1 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x04}}, + } + }) + } + + // L3C Bank 2 for SCL #1 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #1 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x08}}, + } + }) + } + + // MN1 for SCL #1 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0221") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0xb}, + } + }) + } + } + + // Djtag for CPU die #2 (scl #2) + Device (DJT1) { + Name (_HID, "HISI0201") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x60010000, // Min Base Address + 0x6001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + } + }) + + // L3C Bank 0 for SCL #2 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x02}}, + } + }) + } + + // L3C Bank 1 for SCL #2 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x04}}, + } + }) + } + + // L3C Bank 2 for SCL #2 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #2 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x08}}, + } + }) + } + + // MN1 for SCL #2 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0221") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0xb}, + } + }) + } + } +} + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl index 4185f80..af80eb6 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -26,4 +26,6 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP06 ", EFI_ACPI_ARM_O include ("D03Hns.asl") include ("D03Sas.asl") include ("D03Pci.asl") + include ("Apei.asl") + include ("D03UncorePmu.asl") }